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EBD11UD8ADDA-6B 参数 Datasheet PDF下载

EBD11UD8ADDA-6B图片预览
型号: EBD11UD8ADDA-6B
PDF下载: 下载PDF文件 查看货源
内容描述: 1GB DDR SDRAM SO- DIMM ( 128M字64位, 2级) [1GB DDR SDRAM SO-DIMM (128M words x64 bits, 2 Ranks)]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 19 页 / 205 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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DATA SHEET  
1GB DDR SDRAM SO-DIMM  
EBD11UD8ADDA (128M words × 64 bits, 2 Ranks)  
Description  
Features  
The EBD11UD8ADDA is 128M words × 64 bits, 2  
ranks Double Data Rate (DDR) SDRAM Small Outline  
Dual In-line Memory Module, mounting 16 pieces of  
512M bits DDR SDRAM sealed in TCP package. Read  
and write operations are performed at the cross points  
of the CK and the /CK. This high-speed data transfer  
is realized by the 2 bits prefetch-pipelined architecture.  
Data strobe (DQS) both for read and write are available  
for high speed and reliable data bus design. By setting  
extended mode register, the on-chip Delay Locked  
Loop (DLL) can be set enable or disable. This module  
provides high density mounting without utilizing surface  
mount technology. Decoupling capacitors are mounted  
beside each TCP on the module board.  
200-pin socket type small outline dual in line memory  
module (SO-DIMM)  
PCB height: 31.75mm  
Lead pitch: 0.6mm  
2.5V power supply  
Data rate: 333Mbps/266Mbps (max.)  
2.5 V (SSTL_2 compatible) I/O  
Double Data Rate architecture; two data transfers per  
clock cycle  
Bi-directional, data strobe (DQS) is transmitted  
/received with data, to be used in capturing data at  
the receiver  
Data inputs, outputs and DM are synchronized with  
DQS  
4 internal banks for concurrent operation  
Note: Do not push the cover or drop the modules in  
order to avoid mechanical defects, which may  
result in electrical defects.  
(Components)  
DQS is edge aligned with data for READs; center  
aligned with data for WRITEs  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Commands entered on each positive CK edge; data  
referenced to both edges of DQS  
Data mask (DM) for write data  
Auto precharge option for each burst access  
Programmable burst length: 2, 4, 8  
Programmable /CAS latency (CL): 2, 2.5  
Refresh cycles: (8192 refresh cycles /64ms)  
7.8µs maximum average periodic refresh interval  
2 variations of refresh  
Auto refresh  
Self refresh  
Document No. E0431E20 (Ver. 2.0)  
Date Published April 2004 (K) Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2003-2004