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EBD10RD4ADFA-6B 参数 Datasheet PDF下载

EBD10RD4ADFA-6B图片预览
型号: EBD10RD4ADFA-6B
PDF下载: 下载PDF文件 查看货源
内容描述: 注册1GB DDR SDRAM DIMM ( 128M字X72位,1个等级) [1GB Registered DDR SDRAM DIMM (128M words x72 bits, 1 Rank)]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 19 页 / 218 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EBD10RD4ADFA  
DC Characteristics 1 (TA = 0 to +70°C, VDD = 2.5V ± 0.2V, VSS = 0V)  
Parameter  
Symbol  
IDD0  
Grade  
max.  
Unit  
mA  
Test condition  
Notes  
1, 2, 9  
-6B  
-7A, -7B  
3165  
2830  
CKE VIH,  
tRC = tRC (min.)  
Operating current (ACTV-PRE)  
CKE VIH, BL = 4,  
Operating current  
(ACTV-READ-PRE)  
-6B  
-7A, -7B  
3885  
3460  
IDD1  
mA  
CL = 3.5,  
1, 2, 5  
tRC = tRC (min.)  
-6B  
520  
454  
1005  
850  
825  
760  
825  
760  
1635  
1390  
4605  
4000  
4605  
4000  
6225  
5800  
Idle power down standby current  
Floating idle standby current  
Quiet idle standby current  
IDD2P  
IDD2F  
IDD2Q  
IDD3P  
IDD3N  
IDD4R  
IDD4W  
IDD5  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
CKE VIL  
4
-7A, -7B  
-6B  
-7A, -7B  
-6B  
-7A, -7B  
-6B  
-7A, -7B  
-6B  
-7A, -7B  
-6B  
-7A, -7B  
-6B  
-7A, -7B  
-6B  
-7A, -7B  
-6B  
-7A, -7B  
CKE VIH, /CS VIH,  
DQ, DQS, DM = VREF  
CKE VIH, /CS VIH,  
DQ, DQS, DM = VREF  
4, 5  
4, 10  
3
Active power down  
standby current  
CKE VIL  
CKE VIH, /CS VIH  
tRAS = tRAS (max.)  
CKE VIH, BL = 2,  
CL = 3.5  
CKE VIH, BL = 2,  
CL = 3.5  
tRFC = tRFC (min.),  
Input VIL or VIH  
Active standby current  
3, 5, 6  
1, 2, 5, 6  
1, 2, 5, 6  
Operating current  
(Burst read operation)  
Operating current  
(Burst write operation)  
Auto refresh current  
538  
472  
9285  
7780  
Input VDD – 0.2 V  
Input 0.2 V  
Self refresh current  
IDD6  
Operating current  
(4 banks interleaving)  
-6B  
-7A, -7B  
IDD7A  
BL = 4  
1, 5, 6, 7  
Notes. 1. These IDD data are measured under condition that DQ pins are not connected.  
2. One bank operation.  
3. One bank active.  
4. All banks idle.  
5. Command/Address transition once per one cycle.  
6. DQ, DM, DQS transition twice per one cycle.  
7. 4 banks active. Only one bank is running at tRC = tRC (min.)  
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.  
9. Command/Address transition once every two clock cycles.  
10. Command/Address stable at VIH or VIL.  
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)  
(DDR SDRAM Component Specification)  
Parameter  
Symbol  
ILI  
min.  
–2  
max.  
2
Unit  
µA  
Test condition  
Notes  
Input leakage current  
Output leakage current  
Output high current  
Output low current  
VDD VIN VSS  
VDDQ VOUT VSS  
VOUT = 1.95V  
ILO  
–5  
5
µA  
IOH  
IOL  
–15.2  
15.2  
mA  
mA  
VOUT = 0.35V  
Data Sheet E0430E20 (Ver. 2.0)  
11  
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