GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash
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7.33. Enable Reset (66H) and Reset (99H)
If the Reset command is accepted, any on-going internal operation will be terminated and the device will
return to its default power-on state and lose all the current volatile settings, such as Volatile Status Register bits,
Write Enable Latch status (WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), Continuous
Read Mode bit setting (M7-M0) and Wrap Bit Setting (W6-W4). The “Reset (99H)” command sequence as
follow: CS# goes low → Sending Enable Reset command → CS# goes high → CS# goes low → Sending
Reset command → CS# goes high. Once the Reset command is accepted by the device, the device will take
approximately tRST=60µs to reset. During this period, no command will be accepted. Data corruption may
happen if there is an on-going or suspended internal Erase or Program operation when Reset command sequence
is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before
issuing the Reset command sequence.
Figure 38. Enable Reset and Reset command Sequence Diagram
7.34. Read Serial Flash Discoverable Parameter (5AH)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the
functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These
parameter tables can be interrogated by host system software to enable adjustments needed to accommodate
divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC
Standard, JESD68 on CFI. SFDP is a standard of JEDEC Standard No.216.
Figure 39. Read Serial Flash Discoverable Parameter command Sequence Diagram
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