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GD25Q32 参数 Datasheet PDF下载

GD25Q32图片预览
型号: GD25Q32
PDF下载: 下载PDF文件 查看货源
内容描述: [3.3V Uniform Sector Dual and Quad Serial Flash]
分类和应用:
文件页数/大小: 50 页 / 3543 K
品牌: ELM [ ELM ELECTRONICS ]
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GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash  
http://www.elm-tech.com  
7.9. Quad Output Fast Read (6BH)  
The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit  
being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle  
from IO3, IO2, IO1 and IO0. The command sequence is shown in followed Figure10. The first byte addressed  
can be at any location. The address is automatically incremented to the next higher address after each byte of  
data is shifted out.  
Figure 10. Quad Output Fast Read Sequence Diagram  
CS#  
0
1
2
3
4
5
6
7
8
9 10  
28 29 30 31  
SCLK  
Command  
6BH  
24-bit address  
23 22 21  
SI(IO0)  
3
2
1
0
SO(IO1)  
High-Z  
High-Z  
High-Z  
WP#(IO2)  
HOLD#(IO3)  
CS#  
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47  
Dummy Clocks  
SCLK  
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SI(IO0)  
SO(IO1)  
WP#(IO2)  
HOLD#(IO3)  
Byte1 Byte2 Byte3 Byte4  
7.10. Dual I/O Fast Read (BBH)  
The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability  
to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, each bit  
being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle  
from SI and SO. The command sequence is shown in followed Figure11. The first byte addressed can be at any  
location. The address is automatically incremented to the next higher address after each byte of data is shifted  
out.  
Dual I/O Fast Read with “Continuous Read Mode”  
The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous  
Read Mode” bits (M7-4) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4)  
=(1, 0), then the next Dual I/O Fast Read command (after CS# is raised and then lowered) does not require the  
BBH command code. The command sequence is shown in followed Figure12. If the “Continuous Read Mode”  
bits (M5-4) do not equal (1, 0), the next command requires the first BBH command code, thus returning to  
normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before issuing  
normal command.  
Rev.1.0  
50 - 19  
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