GD25LQ40xIGx 1.8V Uniform Sector Dual and Quad Serial Flash
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command → 3-byte address on SI → at least 1 byte data on SI→ CS# goes high. The command sequence is
shown in Figure15. If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes
are sent to device, they are correctly programmed at the requested addresses without having any effects on the
other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched
in; otherwise the Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the
Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is
completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2,
BP1 and BP0) is not executed.
Page Program Sequence Diagram
Figure 15.
Page Program Sequence Diagram (QPI)
Figure 15a.
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13
SCLK
Command
02H
Byte1 Byte2
Byte3
Byte255 Byte256
A23-16 A15-8 A7-0
IO0
20 16 12
8
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO1
IO2
IO3
21 17 13
9
5
6
7
22 18 14 10
23 19 15 11
Rev.1.0
59 - 28
ELM [ ELM ELECTRONICS ]
