EL7564C
Monolithic 4 Amp DC:DC Step-down Regulator
Pin Descriptions
Pin Number
Pin Name
VREF
SGND
COSC
VDD
Pin Function
Bandgap reference bypass capacitor; typically 0.1µF to SGND
1
2
3
4
5
6
7
8
9
Control circuit negative supply or signal ground
Oscillator timing capacitor (see performance curves)
Control circuit positive supply; normally connected to VIN through an RC filter
Junction temperature monitor; connected with 2.2nF to 3.3nF to SGND
VTJ
PGND
PGND
VIN
Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET
Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET
Power supply input of the regulator; connected to the drain of the high-side NMOS power FET
STP
Auxilliary supply tracking positive input; tied to regulator output to synchronize start up with a second supply; leave open
for stand alone operation; 2µA internal pull down current
10
STN
Auxilliary supply tracking negative input; connect to output of a second supply to synchronize start up; leave open for
stand alone operation; 2µA internal pull up current
11
12
13
14
15
16
17
18
19
PGND
PGND
PGND
LX
Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET
Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET
Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET
Inductor drive pin; high current output whose average voltage equals the regulator output voltage
Inductor drive pin; high current output whose average voltage equals the regulator output voltage
Positive supply of high-side driver; boot strapped from VDRV to LX with an external 0.22µF capacitor
Positive supply of low-side driver and input voltage for high side boot strap
LX
VHI
VDRV
PG
Power good window comparator output; logic 1 when regulator output is within ±10% of target output voltage
FB
Voltage feedback input; connected to external resistor divider between VOUT and SGND; a 125nA pull-up current forces
VOUT to SGND in the event that FB is floating
20
EN
Chip enable, active high; a 2µA internal pull up current enables the device if the pin is left open; a capacitor can be added
at this pin to delay the start of converter
4
ELANTEC [ ELANTEC SEMICONDUCTOR ]
