EL5485C, EL5486C - Preliminary
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
Applications Information
Power Supplies and Circuit Layout
The EL5485C and EL5486C comparators operate with
single and dual supply with 5V to 12V between V
S
+ and
V
S
-. The output side of the comparator is supplied by a
single supply from 2.7V to 5V. The rail to rail output
swing enables direct connection of the comparator to
both CMOS and TTL logic circuits. As with many high
speed devices, the supplies must be well bypassed. Elan-
tec recommends a 4.7µF tantalum in parallel with a
0.1µF ceramic. These should be placed as close as possi-
ble to the supply pins. Keep all leads short to reduce
stray capacitance and lead inductance. This will also
minimize unwanted parasitic feedback around the com-
parator. The device should be soldered directly to the PC
board instead of using a socket. Use a PC board with a
good, unbroken low inductance ground plane. Good
ground plane construction techniques enhance stability
of the comparators.
imum slew rate requirements. In some applications, it
may be helpful to apply some positive feedback (hyster-
esis) between the output and the positive input. The
hysteresis effectively causes one comparator's input
voltage to move quickly past the other, thus taking the
input out of the region where oscillation occurs. For the
EL5485C and EL5486C, the propagation delay
increases when the input slew rate increases for low
overdrive voltages. With high overdrive voltages, the
propagation delay does not change much with the input
slew rate.
Latch Pin Dynamics
The EL5486C contains a “transparent” latch for each
channel. The latch pin is designed to be driven with
either a TTL or CMOS output. When the latch is con-
nected to a logic high level or left floating, the
comparator is transparent and immediately responds to
the changes at the input terminals. When the latch is
switched to a logic low level, the comparator output
remains latched to its value just before the latch’s high-
to-low transition. To guarantee data retention, the input
signal must remain the same state at least 1ns (hold time)
after the latch goes low and at least 2ns (setup time)
before the latch goes low. When the latch goes high, the
new data will appear at the output in approximately 6ns
(latch propagation delay). The EL5485C does not have
latch inputs.
Input Voltage Considerations
The EL5485C and EL5486C’s input range is specified
from 0.1V below V
S
- to 2.25V below V
S
+. The criterion
for the input limit is that the output still responds cor-
rectly to a small differential input signal. The differential
input stage is a pair of PNP transistors, therefore, the
input bias current flows out of the device. When either
input signal falls below the negative input voltage limit,
the parasitic PN junction formed by the substrate and the
base of the PNP will turn on, resulting in a significant
increase of input bias current. If one of the inputs goes
above the positive input voltage limit, the output will
still maintain the correct logic level as long as the other
input stays within the input range. However, the propa-
gation delay will increase. When both inputs are outside
the input voltage range, the output becomes unpredict-
able. Large differential voltages greater than the supply
voltage should be avoided to prevent damages to the
input stage.
Hysteresis
Hysteresis can be added externally. The following two
methods can be used to add hysteresis.
Inverting comparator with hysteresis:
V
REF
R
2
R
1
V
IN
+
-
R
3
Input Slew Rate
Most high speed comparators oscillate when the voltage
of one of the inputs is close to or equal to the voltage on
the other input due to noise or undesirable feedback. For
clean output waveform, the input must meet certain min-
9
R
3
adds a portion of the output to the threshold set by R
1
and R
2
. The calculation of the resistor values are as
follows:
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