EL5287C - Preliminary
Dual and Window 4ns High-Speed Comparators
Timing Diagram
Compare
Compare
Latch
Enable
Input
1.4V
Latch
Latch
Latch
Differential
Input
t
s
t
h
t (D)
pw
Voltage
V
IN
V
OS
V
OD
t
-
pd
t +
d
Comparator
Output
2.4V
Definition of Terms
Term
Definition
VOS
VIN
Input Offset Voltage - Voltage applied between the two input terminals to obtain CMOS logic threshold at the output
Input Voltage Pulse Amplitude - Usually set to 1V for comparator specifications
VOD
Input Voltage Overdrive - Usually set to 50mV and in opposite polarity to VIN for comparator specifications
tpd
+
Input to Output High Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS
logic threshold of an output low to high transition
tpd
-
Input to Output Low Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS
logic threshold of an output high to low transition
td+
td-
Latch Disable to Output High Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high
transition to the point of the output crossing CMOS threshold in a low to high transition
Latch Disable to Output Low Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high
transition to the point of the output crossing CMOS threshold in a high to low transition
ts
Minimum Setup Time - The minimum time before the negative transition of the latch signal that an input signal change must be present in
order to be acquired and held at the outputs
th
Minimum Hold Time - The minimum time after the negative transition of the latch signal that an input signal must remain unchanged in
order to be acquired and held at the output
tpw (D)
Minimum Latch Disable Pulse Width - The minimum time that the latch signal must remain high in order to acquire and hold an input signal
change
6
ELANTEC [ ELANTEC SEMICONDUCTOR ]
