EL5283C - Preliminary
EL5283C - Preliminary
Dual and Window 8ns High-Speed Comparators
be tied to ground and the other input can be connected to
some voltage reference (like ±100mV) to avoid oscilla-
tion in the output due to unwanted output to input
feedback.
An approximate equation for the device power dissipa-
tion is as follows. Assume the power dissipation in the
load is very small:
P
DISS
=
(
V
S
×
I
S
+ V
SD
×
I
SD
) ×
N
Input Slew Rate
Most high speed comparators oscillate when the voltage
of one of the inputs is close to or equal to the voltage on
the other input due to noise or undesirable feedback. For
clean output waveform, the input must meet certain min-
imum slew rate requirements. In some applications, it
may be helpful to apply some positive feedback (hyster-
esis) between the output and the positive input. The
hysteresis effectively causes one comparator's input
voltage to move quickly past the other, thus taking the
input out of the region where oscillation occurs. For the
EL5283C, the propagation delay increases when the
input slew rate increases for low overdrive voltages.
With high overdrive voltages, the propagation delay
does not change much with the input slew rate.
where:
V
S
is the analog supply voltage from V
S
+ to V
S
-
I
S
is the analog quiescent supply current per comparator
V
SD
is the digital supply voltage from V
SD
to ground
I
SD
is the digital supply current per comparator
N is the number of comparators in the package
I
SD
strongly depends on the input switching frequency.
Please refer to the performance curve to choose the input
driving frequency. Having obtained the power dissipa-
tion, the maximum junction temperature can be
determined as follows:
T
JMAX
= T
MAX
+
Θ
JA
×
P
DISS
Latch Pin Dynamics
The EL5283C contains a “transparent” latch for each
channel. The latch pin is designed to be driven with
either a TTL or CMOS output. When the latch is con-
nected to a logic high level or left floating, the
comparator is transparent and immediately responds to
the changes at the input terminals. When the latch is
switched to a logic low level, the comparator output
latches remains latched to its value just before the latch
high-to-low transition. To guarantee data retention, the
input signal must remain the same state at least 1ns (hold
time) after the latch goes low and at least 2ns (setup
time) before the latch goes low. When the latch goes
high, the new data will appear at the output in approxi-
mately 8ns (latch propagation delay).
where:
T
MAX
is the maximum ambient temperature
θ
JA
is the thermal resistance of the package
Window Detector
If V
IN
is in the range of V
REFL
< V
IN
< V
REFH
, both out-
puts go high and the input in range is high. If V
IN
is out
of the range set by V
REFH
and V
REFL
, the input in range
is low.
V
REFH
V
IN
V
REFL
Power Dissipation
When switching at high speeds, the comparator's drive
capability is limited by the rise in junction temperature
caused by the internal power dissipation. For reliable
operation, the junction temperature must be kept below
T
JMAX
(125°C).
+
-
OUTH
Input In
Range
+
-
OUTL
8
ELANTEC [ ELANTEC SEMICONDUCTOR ]
