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EL5221C 参数 Datasheet PDF下载

EL5221C图片预览
型号: EL5221C
PDF下载: 下载PDF文件 查看货源
内容描述: 双12MHz的轨至轨输入,输出缓冲器 [Dual 12MHz Rail-to-Rail Input-Output Buffer]
分类和应用:
文件页数/大小: 13 页 / 252 K
品牌: ELANTEC [ ELANTEC SEMICONDUCTOR ]
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EL5221C  
Dual 12MHz Rail-to-Rail Input-Output Buffer  
Driving Capacitive Loads  
Power Supply Bypassing and Printed Circuit  
Board Layout  
The EL5221C can drive a wide range of capacitive  
loads. As load capacitance increases, however, the -3dB  
bandwidth of the device will decrease and the peaking  
increase. The buffers drive 10pF loads in parallel with  
10kwith just 1.5dB of peaking, and 100pF with 6.4dB  
of peaking. If less peaking is desired in these applica-  
tions, a small series resistor (usually between 5and  
50) can be placed in series with the output. However,  
this will obviously reduce the gain slightly. Another  
method of reducing peaking is to add a "snubber" circuit  
at the output. A snubber is a shunt load consisting of a  
resistor in series with a capacitor. Values of 150and  
10nF are typical. The advantage of a snubber is that it  
does not draw any DC load current or reduce the gain  
The EL5221C can provide gain at high frequency. As  
with any high frequency device, good printed circuit  
board layout is necessary for optimum performance.  
Ground plane construction is highly recommended, lead  
lengths should be as short as possible, and the power  
supply pins must be well bypassed to reduce the risk of  
oscillation. For normal single supply operation, where  
the VS- pin is connected to ground, a 0.1µF ceramic  
capacitor should be placed from VS+ to pin to VS- pin. A  
4.7µF tantalum capacitor should then be connected in  
parallel, placed in the region of the buffer. One 4.7µF  
capacitor may be used for multiple devices. This same  
capacitor combination should be placed at each supply  
pin to ground if split supplies are to be used.  
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