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EL4585CS 参数 Datasheet PDF下载

EL4585CS图片预览
型号: EL4585CS
PDF下载: 下载PDF文件 查看货源
内容描述: 水平同步锁相, 8 FSC [Horizontal Genlock, 8 FSC]
分类和应用: 晶体时钟发生器微控制器和处理器外围集成电路光电二极管局域网
文件页数/大小: 16 页 / 264 K
品牌: ELANTEC [ ELANTEC SEMICONDUCTOR ]
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EL4585C  
Horizontal Genlock, 8 F  
SC  
e
e
25 C unless otherwise noted)  
AC Electrical Characteristics (V  
5V, T  
§
DD  
A
Test  
Parameter  
Conditions  
Temp  
Min  
Typ  
Max  
Units  
Level  
@
VCO Gain 20 MHz  
Test circuit 1  
25 C  
§
15.5  
V
V
V
V
dB  
dB  
ns  
e
H-sync S/N Ratio  
Jitter  
V
DD  
5V (Note 2)  
25 C  
§
35  
VCXO Oscillator  
25 C  
§
1
Jitter  
LC Oscillator (Typ)  
25 C  
§
10  
ns  
Note 2: Noisy video signal input to EL4583C, H-sync input to EL4585C. Test for positive signal lock.  
Pin Description  
Pin No.  
Pin Name  
Function  
N value for internal counter. See table below for values.  
d
Digital inputs to select  
16, 1, 2  
Prog A,B,C  
3
4
5
6
7
Osc/VCO Out  
Output of internal inverter/oscillator. Connect to external crystal or LC tank VCO circuit.  
Analog positive supply for oscillator, PLL circuits.  
Input from external VCO.  
V
(A)  
DD  
Osc/VCO In  
(A)  
V
SS  
Analog ground for oscillator, PLL circuits.  
l
Connect to loop filter. If the H-sync phase is leading or H-sync frequency CLK 2N, current is  
pumped into the filter capacitor to increase VCO frequency. If H-sync phase is lagging or frequency  
d
Charge Pump  
Out  
k
d
CLK 2N, current is pumped out of the filter capacitor to decrease VCO frequency. During coast  
mode or when locked, charge pump goes to a high impedance state.  
8
9
Div Select  
Divide select input. When high, the internal divider is enabled and EXT DIV becomes a test pin,  
d
outputting CLK 2N. When low, the internal divider is disabled and EXT DIV is an input from an  
d
external N.  
k
e
e
fast lock mode,  
Coast  
Tri-state logic input. Low( (/3*V  
)
CC  
normal mode, Hi Z(or (/3 to )/3*V  
)
CC  
l
e
coast mode.  
High( )/3*V )  
CC  
10  
11  
12  
13  
14  
15  
H-sync In  
Horizontal sync pulse (CMOS level) input.  
Positive supply for digital, I/O circuits.  
V
DD  
(D)  
Lock Det  
Ext Div  
Lock Detect output. Low level when PLL is locked. Pulses high when out of lock.  
d
External Divide input when DIV SEL is low, internal  
Ground for digital, I/O circuits.  
2N output when DIV SEL is high.  
V
SS  
(D)  
CLK Out  
Buffered output of the VCO.  
Table 5. VCO Divisors  
Prog A  
Pin 16  
Prog B  
Pin 1  
Prog C  
Pin 2  
Div Value  
N
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1702  
1728  
1888  
2270  
1364  
1716  
1560  
1820  
3
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