EL4583C
Sync Separator, 50% Slice, S-H, Filter, H
OUT
then self-timed out. In the absence of a serration pulse,
an internal timer will default the start of vertical.
The Horizontal circuit senses C/S edges and produces
the true horizontal pulses of nominal width 5µs. The
leading edge is triggered from the leading edge of the
input H sync, with the same prop. delay as composite
sync. The half line pulses present in the input signal dur-
ing vertical blanking are removed with an internal 2H
eliminator circuit. The 2H eliminator initiates a time out
period after a horizontal pulse is generated. The time out
period is a function of IOT which is set by RSET.
The back porch is triggered from the sync tip trailing
edge and initiates a one-shot pulse. The period of this
pulse is again a function of IOT and will therefore track
the scan rate set by RESET.
The odd/even circuit (O/E) tracks the relationship of the
horizontal pulses to the leading edge of the vertical out-
put and will switch on every field at the start of vertical.
Pin 13 is high during an odd field.
Loss of video signal can be detected by monitoring the
No Signal Detect Output pin 10. The VTIP voltage held
by the sample and hold is compared with a voltage level
set by RLV on pin 2. Pin 10 output goes high when the
VTIP falls below RLV set value.
VTIP voltage is also passed through an amplifier with
gain of 2 and buffed to pin 9. This provides an indication
of signal strength. This signal (Level Output) can be
used for AGC applications.
10
ELANTEC [ ELANTEC SEMICONDUCTOR ]
