EL4581C
Sync Separator 50% Slice S-H Filter
Description of Operation
A simplified block schematic is shown in Figure
2 The following description is intended to pro-
vide the user with sufficient information to be
able to understand the effects that the external
components and signal conditions have on the
outputs of the integrated circuit
The video signal is AC coupled to pin 2 via the
capacitor C
1
nominally 0 1
mF
The clamp circuit
A1 will prevent the input signal on pin 2 going
any more negative than 1 5V the value of refer-
ence voltage V
R1
Thus the sync tip the most
negative part of the video waveform will be
clamped at 1 5V The current source I
1
nominal-
ly 10
mA
charges the coupling capacitor during
the remaining portion of the H line approxi-
mately 58
ms
for a 15 75 kHz timebase From
I
t
e
C
V the video time-constant can be
calculated It is important to note that the charge
taken from the capacitor during video must be
replaced during the sync tip time which is much
shorter (ratio of x 12 5) The corresponding cur-
rent to restore the charge during sync will there-
fore be an order of magnitude higher and any
resistance in series with C
I
will cause sync tip
crushing For this reason the internal series re-
sistance has been minimized and external high
resistance values in series with the input cou-
pling capacitor should be avoided The user can
exercise some control over the value of the input
time constant by introducing an external pull-up
resistance from pin 2 to the 5V supply The maxi-
mum voltage across the resistance will be V
DD
less 1 5V for black level For a net discharge cur-
rent greater than zero the resistance should be
greater than 450k This will have the effect of
increasing the time constant and reducing the de-
gree of picture tilt The current source I
1
directly
tracks reference current I
TR
and thus increases
with scan rate adjustment as explained later
The signal is processed through an active 3 pole
filter (F1) designed for minimum ripple with con-
stant phase delay The filter attenuates the color
burst by 24 dB and eliminates fast transient
spikes without sync crushing An external filter
is not necessary The filter also amplifies the
video signal by 6 dB to improve the detection
accuracy Note that the filter cut-off frequency is
a function of RSET through I
OT
and is propor-
tional to I
OT
Internal reference voltages (block V
REF
) with
high immunity to supply voltage variation are
derived on the chip Reference V
R4
with op-amp
A2 forces pin 6 to a reference voltage of 1 7V
nominal Consequently it can be seen that the
external resistance RSET will determine the val-
ue of the reference current I
TR
The internal re-
sistance R3 is only about 6 kX much less than
RSET All the internal timing functions on the
chip are referenced to I
TR
and have excellent
supply voltage rejection
Comparator C2 on the input to the sample and
hold block (S H) compares the leading and trail-
ing edges of the sync pulse with a threshold volt-
age V
R2
which is referenced at a fixed level above
the clamp voltage V
R1
The output of C2 initiates
the timing one-shots for gating the sample and
hold circuits The sample of the sync tip is de-
layed by 0 8
ms
to enable the actual sample of
2
ms
to be taken on the optimum section of the
sync pulse tip The acquisition time of the circuit
is about three horizontal lines The double poly
CMOS technology enables long time constants to
be achieved with small high quality on-chip ca-
pacitors The back porch voltage is similarly de-
rived from the trailing edge of sync which also
serves to cut off the tip sample if the gate time
exceeds the tip period Note that the sample and
hold gating times will track RSET through I
OT
The 50% level of the sync tip is derived through
the resistor divider R1 and R2 from the sample
and held voltages V
TIP
and V
BP
and applied to
the plus input of comparator C1 This compara-
tor has built in hysteresis to avoid false trigger-
ing The output of C2 is a digital 5V signal which
feeds the C S ouput buffer B1 and the other in-
ternal circuit blocks the vertical back porch and
odd even functions
The vertical circuit senses the C S edges and ini-
tiates an integrator which is reset by the shorter
horizontal sync pulses but times out the longer
8
ELANTEC [ ELANTEC SEMICONDUCTOR ]
