EL2150C/EL2157C
125 MHz Single Supply, Clamping Op Amps
For other biasing conditions see the Differential
Gain and Differential Phase vs. Input Voltage
curves.
Applications Information Ð Contd.
As far as the output stage of the amplifier is con-
a
gains other than
cerned, R
R
appear in parallel with R for
G L
F
a
1. As this combination gets
Output Drive Capability
In spite of their moderately low 5 mA of supply
current, the EL2150C/EL2157C are capable of
smaller, the bandwidth falls off. Consequently,
has a minimum value that should not be ex-
ceeded for optimum performance.
R
F
g
providing 100 mA of output current into a 10X
g
load, or 60 mA into 50X. With this large output
e a
e
F
e
0X is optimum. For Av
1 or 2 (noise gain of 2), optimum response is
For A
b
1, R
V
a
current capability, a 50X load can be driven to
e
choice for driving isolation transformers in tele-
g
g
5V, making it an excellent
3V with V
S
obtained with R between 500X and 1 kX. For
F
e b
a
4 or 5 (noise gain of 5), keep R be-
F
Av
communications applications.
tween 2 kX and 10 kX.
Driving Cables and Capacitive Loads
Video Performance
When used as a cable driver, double termination
is always recommended for reflection-free per-
formance. For those applications, the back-termi-
nation series resistor will de-couple the
EL2150C/EL2157C from the cable and allow ex-
tensive capacitive drive. However, other applica-
tions may have high capacitive loads without a
back-termination resistor. In these applications, a
small series resistor (usually between 5X and
50X) can be placed in series with the output to
For good video performance, an amplifier is re-
quired to maintain the same output impedance
and the same frequency response as DC levels are
changed at the output. This can be difficult when
driving a standard video load of 150X, because of
the change in output current with DC level. Dif-
ferential Gain and Differential Phase for the
EL2150C/EL2157C are specified with the black
a
level of the output video signal set to
1.2V.
This allows ample room for the sync pulse even
eliminate most peaking. The gain resistor (R )
G
a
in a gain of 2 configuration. This results in dG
and dP specifications of 0.05% and 0.05 while
can then be chosen to make up for any gain loss
which may be created by this additional resistor
at the output.
§
a
driving 150X at a gain of 2. Setting the black
level to other values, although acceptable, will
compromise peak performance. For example,
looking at the single supply dG and dP curves for
Disable/Power-Down
The EL2157C amplifier can be disabled, placing
its output in a high-impedance state. The disable
or enable action takes only about 40 nsec. When
disabled, the amplifier’s supply current is re-
duced to 0 mA, thereby eliminating all power
consumption by the EL2157C. The EL2157C am-
plifier’s power down can be controlled by stan-
dard CMOS signal levels at the ENABLE pin.
The applied CMOS signal is relative to the GND
e
duced from 1.2V to 0.6V dG/dP will increase
R
L
150 X, if the output black level clamp is re-
from 0.05%/0.05 to 0.08%/0.25 Note that in a
§
§
a
gain of 2 configuration, this is the lowest black
level allowed such that the sync tip doesn’t go
below 0V.
If your application requires that the output goes
to ground, then the output stage of the
EL2150C/EL2157C, like all other single supply
op amps, requires an external pull down resistor
tied to ground. As mentioned above, the current
flowing through this resistor becomes the DC
bias current for the output stage NPN transistor.
As this current approaches zero, the NPN turns
off, and dG and dP will increase. This becomes
more critical as the load resistor is increased in
value. While driving a light load, such as 1 kX, if
the input black level is kept above 1.25V, dG and
a
pin. For example, if a single 5V supply is used,
a
a
the logic voltage levels will be 0.5V and 2.0V.
If using dual 5V supplies, the logic levels will
g
b
b
be 4.5V and 3.0V. Letting the ENABLE pin
float will disable the EL2157C. If the power-
down feature is not desired, connect the EN-
ABLE pin to the V
a
levels of 0.8V and 2.0V, so care must be tak-
en if standard TTL will be used to drive the EN-
ABLE pin.
pin. The guaranteed logic
levels of 0.5V and 2.0V are not standard TTL
a
S
a
a
a
dP are a respectable 0.03% and 0.03 .
§
13
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