EL2090C
100 MHz DC-Restored Video Amplifier
Applications Information
Contd
The HOLD input to the sample-and-hold has a
1 4V threshold and is clamped to a diode below
ground and 6V above ground The hold step char-
acteristics are not sensitive to logic high nor low
levels (within TTL or CMOS swings) but logic
slewrates greater than 1000V
ms
can couple noise
and hold step into the sample-to-hold output
waveforms The logic slewrate should be greater
than 50V
ms
to avoid hold jitter To avoid artifi-
cially high droop in hold mode the Chold pin
and Chold itself should be guarded with circuit
board traces connected to the output of the sam-
ple-and-hold Low-leakage hold capacitors should
be used such as mica or mylar but not ceramic
The excellent properties of more expensive poly-
styrene polypropylene or teflon capacitors are
not needed
hold step and increasing Chold is the most di-
rect way to do this Increasing Chold also re-
duces the slew rate of the sample and hold sec-
tion but because of the limited size of the vid-
eo signal this is usually not a limitation
2 A sampling interval (dictated by the HOLD
pin) that is too small By small we mean less
than 2
ms
For a sampling interval that is wide enough
there is enough time for the loop to close and for
the amplifier to discharge whatever charge was
dumped onto Chold it during the initial power
spike and to then ramp up (or down) to the volt-
age that is proper for a balanced loop When the
sampling interval is too small there is insuffi-
cient time for internal devices to recover from
their initial saturated state from power-up be-
cause the feedback is not closed long enough
Therefore typical recovery times for the loop are
2
ms
or greater Summarizing the two things
that could prevent proper saturation recovery are
(as mentioned above) too large a capacitor which
slows the charge and discharge rate of the stored
voltage at Chold and too small a sampling inter-
val in which the entire feedback loop is closed
The circuit shown below prevents the fault condi-
tion from occurring by preventing the node from
ever saturating By clamping the value of Chold
to some value lower than the supply voltage less
The user should be aware of a combination of
conditions that may make the EL2090 operate in-
correctly upon power-up The fault condition can
be described by noticing that the sample-and-
hold output (pin 11) appears locked at a voltage
close to V
CC
This voltage is maintained regard-
less of changes at the inputs to the sample-and-
hold (pins 5 and 6) or to the HOLD control input
(pin 7) Two conditions must occur to bring this
about
1 A large value of Chold usually values of
1000 pF or more This is not an unusual situa-
tion Many users want to reduce the size of the
2090 – 13
8
ELANTEC [ ELANTEC SEMICONDUCTOR ]
