EL2005/EL2005C
High Accuracy Fast Buffer
Resistor values may be predicted by:
Applications Information
a
b
V
V
Recommended Layout Precautions
j
e
R
LIM
RF/video printed circuit board layout rules
should be followed when using the EL2005 since
it will provide power gain to frequencies over
100 MHz. Ground planes are recommended and
power supplies should be decoupled at each de-
vice with low inductance capacitors. In addition,
ground plane shielding may be extended to the
metal case of the device since it is electrically iso-
lated from internal circuitry. Alternatively, the
case should be connected to the output to mini-
mize input capacitance.
I
I
SC
SC
s
where: I
100 mA for EL2005
SC
The inclusion of limiting resistors in the collec-
tors of the output transistors reduces output volt-
age swing. Decoupling V
capacitors to ground will retain full output swing
for transient pulses. An alternate active current
limit technique that retains full DC output swing
is also shown on page 4. In this circuit, the cur-
rent sources are saturated during normal opera-
a
b
and V
pins with
C
C
Offset Voltage Adjustment
tion thus applying full supply voltage to the V
C
The EL2005’s offset voltages have been actively
trimmed by laser to meet guaranteed specifica-
tions when the offset preset pin is shorted to the
offset adjust pin. The pre-calibration allows the
devices to be used in most DC or AC applications
without individually offset nulling each device. If
offset null is desirable, it is simply obtained by
leaving the offset preset pin open and connecting
a trim pot of 200X between the offset adjust pin
pins. Under fault conditions, the voltage decreas-
es as required by the overload.
V
0.6V
BE
j
e
e
10X
R
LIM
I
60 mA
SC
Capacitive Loading
The EL2005 is designed to drive capacitive loads
such as coaxial cables in excess of several thou-
sand picofarads without susceptibility to oscilla-
tion. However, peak current resulting from
b
and V as illustrated on page 4.
Operation from Single or Asymmetrical
Power Supplies
c
maximum peak current ratings for the devices.
(C
dV/dt) should be limited below absolute
This device type may be readily used in applica-
tions where symmetrical supplies are unavailable
or not desirable. In this case, an apparent output
offset occurs due to the device’s voltage gain of
less than unity. This additional output offset er-
ror may be predicted by:
Thus:
DV
IN
s
s
g
c
C
I
250 mA
L
OUT
Dt
In addition, power dissipation resulting from
driving capacitive loads plus standby power
should be kept below the total package power
rating:
ab
b
)
(V
V
j
b
e
ab b
0.005 (V V )
DV
(1 A )
V
O
2
e
where: A
No load voltage gain, typically 0.99
Positive supply voltage
Negative supply voltage
V
ae
t
t
a
P
AC
V
V
P pkg
D
P
DC
be
a b
b
c
a
I P
S
P pkg
D
(V
V
f
)
AC
a
e
a
b e
For example, with V
5V and V
b
justed to zero as described above.
b
12V, DV would be 35 mV. This may be ad-
2
j
c
c
C
O
P
(V
)
AC
P-P
L
e
where: V
Peak-to-peak output voltage
swing
Short Circuit Protection
P-P
In order to optimize transient response and out-
put swing, output current limit has been omitted
from the EL2005. Short circuit protection may be
added by inserting appropriate value resistors be-
e
f
Frequency
Load Capacitance
e
C
L
a
tween V and V
as shown on page 4.
a
b
b
pins and V and V pins
C
C
7
ELANTEC [ ELANTEC SEMICONDUCTOR ]
