EL1056AC/EL1056C
Monolithic High-Speed Pin Driver
Applications Information
Functional Description
The EL1056 is a fully integrated pin driver for
automatic test systems. Pin drivers are essential-
ly pulse generators whose high and low levels can
be externally programmed and accurately switch-
ed in time, as well as incorporating an output
switch to disconnect the driver from a measure-
ment bus. Additionally, the EL1056 has pro-
grammable slewrate.
1056–2
Control Voltage Inputs
The analog level inputs are named V
and
, and the output replicates them as con-
INH
V
INL
trolled by logic inputs. The analog inputs are
buffered and have bandwidths of 35 MHz and
slewrates of 25V/ms. For full slewrate, 4V of
headroom should be given to the inputs, that is
1056–3
a
a
or B , and
should be 4V more positive than V or
Alternate Logic Interface
V
V
B
should be 4V less than V
INH
b
Figure 1
INL
b
e
. At lower slewrates (I
500 mA or less),
SR
3V of headroom will suffice. Insufficient head-
room causes distorted output waveforms or delay
Slewrate Control
The slewrate is controlled by the I input. This
SR
is a current input and scales the output slewrate
by a nominal 1.25V/ns/mA. The slewrate main-
tains calibration and symmetry to at least as slow
errors in output transitions. V
in voltage than V
may be lower
, but the output will not fol-
INH
INL
low the control logic correctly. Furthermore,
should be 200 mV more positive than V
V
INH
INL
as 0.2V/ns. The practical upper end of I is
SR
1 mA, and supply current increases with increas-
(the minimum output amplitude) for accurate
switching.
ing I
.
SR
Logic Inputs
The I
control can be used to adjust individual
SR
The logic inputs are all differential types, with
both NPN and PNP transistors connected to
each terminal. They are optimized for differential
pin drivers to a system standard, by adjusting
the value of its series resistor. Slewrate can also
be slowed to reduce output ringing and crosstalk.
a
b
ECL drive, which optimizes
to
edge delay
time matching. Larger logic levels can introduce
feedthrough glitches into the output waveform.
For CMOS input logic levels, an ECL output
waveform will show feedthrough when the
input risetime is shorter than 8 ns, differential or
single-ended. CMOS output swings show less ab-
erration, and the EL1056 can tolerate a 4 ns
single-ended risetime or 2 ns risetime for differ-
ential inputs. Attenuating CMOS or TTL inputs
to 1 Vp-p will eliminate all logic feedthrough as
shown in Figure 1.
With ECL output swings, there is not enough
voltage excursion to incur slewrate delays to 50%
logic threshold. The risetime, delays, and disper-
sions do not degrade with reasonably reduced
I
SR
, and overshoot will reduce markedly. An I
SR
of 350 mA produces a very good ECL output, and
driver dissipation is also reduced.
9
ELANTEC [ ELANTEC SEMICONDUCTOR ]
