dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
TABLE 2:
PIN NAMES: dsPIC33EP256MU810 AND dsPIC33EP512MU810
(1,2)
DEVICES
(CONTINUED)
Pin
Number
Pin
Number
Full Pin Name
Full Pin Name
E1
E2
E3
E4
E5
E6
E7
K4
K5
K6
K7
K8
K9
K10
K11
L1
AN19/PWM6H/RPI52/RC4
AN18/PWM6L/RPI51/RC3
J8
J9
No Connect
No Connect
RP104/RF8
C1IN3-/SCK2/PMA5/RP118/RG6
AN17/PWM5H/RPI50/RC2
No Connect
J10
J11
K1
K2
K3
L3
(5)
D-/RG3
PGEC3/AN1/RPI33/RB1
PGED3/AN0/RPI32/RB0
VREF+/RA10
RP113/RG1
No Connect
AN8/PMA6/RPI40/RB8
No Connect
AVSS
L4
AN9/PMA7//RPI41/RB9
AN10/CVREF/PMA13/RPI42/RB10
RP109/RF13
RP108/RF12
L5
AN14/PMA1/RPI46/RB14
VDD
L6
L7
AN13/PMA10/RPI45/RB13
AN15/PMA0/RPI47/RB15
RPI78/RD14
RP79/RD15
L8
USBID/RP99/RF3
RP98/RF2
L9
(3)
L10
L11
SDA2 /PMA9/RP100/RF4
(3)
PGEC1/AN6/RPI38/RB6
VREF-/RA9
SCL2 /PMA8/RP101/RF5
L2
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 “Peripheral Pin Select” for
available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section 11.0 “I/O Ports” for more information.
2
3: The availability of I C™ interfaces varies by device. Selection (SDAx/SCLx or ASDAx/ASCLx) is made using the device Configuration bits,
ALTI2C1 and ALTI2C2 (FPOR<5:4>). See Section 29.0 “Special Features” for more information.
4: The pin name is SCL1/RG2 for the dsPIC33EP512(GP/MC)806 and PIC24EP512GP806 devices.
5: The pin name is SDA1/RG3 for the dsPIC33EP512(GP/MC)806 and PIC24EP512GP806 devices.
2009-2012 Microchip Technology Inc.
DS70616G-page 13
EFC [ Electronic Film Capacitors, Inc. ]
