TEST CONFIGURATIONS
DESIGN CONSIDERATIONS
TO OSCILLOSCOPE
Input Source Impedance
L
To maintain low-noise and ripple at the input voltage, it is
critical to use low ESR capacitors at the input to the
module. Figure 20 shows the input ripple voltage
(mVp-p) for various output models using 6x47uF low
ESR tantalum capacitors (SANYO P/N:16TQC47M,
47uF/16V or equivalent) and 6x22 uF very low ESR
ceramic capacitors (TDK P/N:C3225X7S1C226MT,
22uF/16V or equivalent).
V(+)
I
100uF
Tantalum
2
BATTERY
VI(-)
Note: Input reflected-ripple current is measured with a
simulated source inductance. Current is
measured at the input of the module.
The input capacitance should be able to handle an AC
ripple current of at least:
Figure 17: Input reflected-ripple test setup
Vout
Vin
Vout
Vin
⎛
⎜
⎞
⎟
Irms = Iout
1 −
Arms
⎝
⎠
COPPER STRIP
Vo
350
300
250
200
150
100
50
Resistive
Load
1uF
10uF
tantalum ceramic
SCOPE
GND
Note: Use a 10µF tantalum and 1µF capacitor. Scope
measurement should be made using a BNC
connector.
Tantalum
Ceramic
Figure 18: Peak-peak output noise and startup transient
0
0
measurement test setup
1
2
3
4
5
6
CONTACT AND
Output Voltage (Vdc)
DISTRIBUTION LOSSES
VI
Vo
I
Io
Figure 20: Input ripple voltage for various output models,
Io = 16A (Cin = 6x47uF tantalum capacitors and
6x22uF ceramic capacitors at the input)
LOAD
SUPPLY
GND
CONTACT RESISTANCE
Figure 19: Output voltage and efficiency measurement test
setup
Note: All measurements are taken at the module
terminals. When the module is not soldered (via
socket), place Kelvin connections at module
terminals to avoid measurement errors due to
contact resistance.
Vo× Io
Vi × Ii
η = (
)×100 %
DS_DNL10SIP16_01262007
6
DELTA [ DELTA ELECTRONICS, INC. ]
