DP805x Instructions set details
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3.8.
CPL
3.8.1. CPL A
Function:
Complement accumulator
Description: Each bit of the accumulator is logically complemented (one’s
complement). Bits which previously contained a one are changed to
zero and vice versa. No flags are affected.
Operation: (PC) ← (PC) + 1
(A) ← / (A)
Bytes:
Cycles:
1
1
Encoding:
1
1
1
1
0
1
0
0
3.8.2. CPL BIT
Function:
Complement bit
Description: The bit variable specified is complemented. A bit which had been a one
is changed to zero and vice versa. No other flags are affected. CPL can
operate on the carry or any directly addressable bit.
Note:
When this instruction is used to modify an output pin, the value used as
the original data will be read from the output data latch, not the input
pin.
Operation: (PC) ← (PC) + 2
(C) ← (bit)
Bytes:
Cycles:
2
3
Encoding:
1
0
1
1
0
0
1
0
bit address
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