tation. It also permits FPGA prototyping be-
fore ASIC production.
B L O C K D I A G R A M
Unlimited Designs license allows using IP
Core in unlimited number of FPGA bitstreams
and ASIC implementations.
datao(31:0)
adatai(31:0)
bdatai(31:0)
Arguments
Checker
Result
Composer
Main FP
Pipelined Unit
ofo
ufo
ifo
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time of use
limitations.
en
rst
clk
Arguments Checker - performs input data
analyze against IEEE-754 number standard
compliance. The appropriate numbers and
information about the input data classes are
given as the results to Main FP Pipelined
Unit.
● Single Design license for
○ VHDL, Verilog source code called HDL
Source
○ Encrypted, or plain text EDIF called Netlist
● Unlimited Designs license for
○ HDL Source
Main FP Pipelined Unit - performs floating
point multiply function. Gives the complex
information about the results and makes final
flags settings.
○ Netlist
● Upgrade from
○ Netlist to HDL Source
○ Single Design to Unlimited Designs
S Y M B O L
Result Composer - performs result rounding
function, data alignment to IEEE-754 stan-
dard, and the final flags setting.
adatai(31:0) datao(31:0)
bdatai(31:0)
ofo
ufo
ifo
P E R F O R M A N C E
The following table gives a survey about the
Core area and performance in the ALTERA®
devices after Place & Route :
en
rst
clk
Speed
grade
-1
P I N S D E S C R I P T I O N
Device
Logic Cells
Fmax
PIN
TYPE
DESCRIPTION
FLEX10KE
ACEX1K
APEX20K
APEX20KE
APEX20KC
APEX-II
MERCURY
STRATIX
CYCLONE
STRATIX-II
CYCLONE-II
1- 9-bit DSP block
1340
1340
1210
1210
1210
40 MHz
40 MHz
50 MHz
50 MHz
51 MHz
67 MHz
77 MHz
93 MHz
72 MHz
134 MHz
117 MHz
-1
-1
-1
-7
-7
-5
-5
-6
clk
rst
en
Input Global system clock
Input Global system reset
Input Enable computing
Input A data bus input
Input B data bus input
Output Data bus output
Output Overflow flag
1210
adatai[31:0]
bdatai[31:0]
datao[31:0]
ofo
1290
440+8M1
1170
-3
-6
410+8M1
480+8M1
ufo
Output Underflow flag
Output Invalid result flag
Core performance in ALTERA® devices
ifo
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are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
