Unlimited Designs license allows using IP
Core in unlimited number of FPGA bitstreams
and ASIC implementations.
B L O C K D I A G R A M
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time of use
limitations.
datao(31:0)
Argument
Checker
Result
Composer
Main FP
Pipelined Unit
datai(31:0)
ofo
ufo
ifo
en
rst
clk
● Single Design license for
○ VHDL, Verilog source code called HDL
Source
Arguments Checker - performs input data
analyze against IEEE-754 number standard
compliance. The appropriate numbers and
information about the input data classes are
given as the results to Main FP Pipelined
Unit.
○ Encrypted, or plain text EDIF called Netlist
● Unlimited Designs license for
○ HDL Source
○ Netlist
● Upgrade from
Main FP Pipelined Unit - performs floating
point to integer conversion. Gives the com-
plex information about the results to Result
Composer module.
○ Netlist to HDL Source
○ Single Design to Unlimited Designs
S Y M B O L
datao(31:0)
datai(31:0)
Result Composer - performs result rounding
function, data alignment to IEEE-754 stan-
dard, and the final flags setting.
ofo
ufo
ifo
en
rst
clk
P I N S D E S C R I P T I O N
PIN
TYPE
DESCRIPTION
clk
rst
en
Input Global system clock
Input Global system reset
Input Enable computing
Input Data bus input
datai[31:0]
datao[31:0]
ofo
Output Data bus output
Output Overflow flag
ufo
Output Underflow flag
Output Invalid result flag
ifo
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