LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of
IP Core easy and simply.
Single Design
license allows use IP Core in
single FPGA bitstream and ASIC implemen-
tation.
Unlimited Designs, One Year
licenses allow
use IP Core in unlimited number of FPGA
bitstreams and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time restric-
tion except
One Year
license where time of
use is limited to 12 months.
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PINS DESCRIPTION
PIN
rst
datai(7:0)
addr(1:0)
cs
rd
wr
clk0
gate0
clk1
gate1
clk2
gate2
datao(7:0)
out0
out1
out2
TYPE
input
input
input
input
input
input
input
input
input
input
input
input
DESCRIPTION
Global reset
Processor data bus (input)
Processor address lines
Chip select
Processor read strobe
Processor write strobe
Clock input for Counter 0
Gate input for Counter 0
Clock input for Counter 1
Gate input for Counter 1
Clock input for Counter 2
Gate input for Counter 2
Single Design license for
VHDL, Verilog source code called HDL
Source
Encrypted, or plain text EDIF called Netlist
output Processor data bus (output)
output Output of Counter 0
output Output of Counter 1
output Output of Counter 2
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One Year license for
Encrypted Netlist only
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Unlimited Designs license for
HDL Source
Netlist
BLOCK DIAGRAM
rst
addr(1:0)
wr
rd
cs
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Upgrade from
HDL Source to Netlist
Single Design to Unlimited Designs
Read/Write
Logict
Counter 0
clk0
gate0
out0
datai(7:0)
SYMBOL
rst
datai(7:0)
addr(1:0)
cs
rd
wr
clk0
gate0
clk1
gate1
clk2
gate2
out0
out1
datao(7:0)
datao(7:0)
Data Bus
Buffer
Counter 1
clk1
gate1
out1
clk1
gate1
out1
Control Word
Register
Counter 2
out2
Read Write Logic
- The Read/Write Logic
accepts inputs from the system bus and gen-
erates control signals for the other functional
blocks of the D8254. ADDR(1:0) select one of
the three counters or the Control Word Regis-
ter to be read from/written into. A “low'' on the
RD input tells the D8254 that the CPU is
reading one of the counters. A “low'' on the
WR input tells the D8254 that the CPU is writ-
ing either a Control Word or an initial count.
Both RD and WR are qualified by CS; RD
and WR are ignored unless the 82C54 has
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Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
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