DM9302
10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus
6.51 Memory Data Write Command with Address Increment Register (F8H)
When register FFH bit 7 is “0”, register FBH value will be returned to 0000H, if 16K-byte boundary is reached.
Bit
Name
Default
Description
7:0
MWCMD
X,WO
Write Data to TX SRAM
After the write of this command, the write pointer is increased by 1, 2, or 4, depends
on the operator mode. (8-bit, 16-bit,32-bit respectively)
6.52 Memory Data Write Address Register (FAH)
When register FFH bit 7 is “0”, register FBH and FAH can be used as memory byte address to write internal 64K-byte
memory.
When register FFH bit 7 is “1”, register FBH and FAH are reserved. The processor port transmit memory address is generated
by DM9302 automatically.
Bit
Name
Default
Description
7:0
MDWAL
PHS0,RW Memory Data Write_ address Low Byte[7:0]
6.53 Memory Data Write Address Register (FBH)
Bit
Name
Default
Description
7:0
MDWAH
PHS0,RW Memory Data Write Byte Address High Byte[15:8]
6.54 TX Packet Length Registers (FCH~FDH)
Bit
7:0
7:0
Name
TXPLH
TXPLL
Default
Description
Description
PHS0,RW TX Packet Length High byte
PHS0,RW TX Packet Length Low byte
6.55 Interrupt Status Register (FEH)
Bit
Name
Default
7
IOMODE
T0, RO
Width Processor Data Bus
0: 16-bit mode
1: 8-bit mode
6
5
4
3
2
1
0
RESERVED
LNKCHG
CNT_ERR
ROO
PHS0,RO
Reserved
PHS0,RW/C1 Link Status Change of port 0 or 1
PHS0,RW/C1 Memory Management error
PHS0,RW/C1 Receive Overflow Counter Overflow
PHS0,RW/C1 Receive Overflow
PHS0,RW/C1 Packet Transmitted
PHS0,RW/C1 Packet Received
ROS
PT
PR
6.56 Interrupt Mask Register (FFH)
Bit
7
6
5
4
3
2
1
0
Name
TXRX_EN
RESERVED
LNKCHGI
CNT_ERR
ROOI
Default
PHS0,RW
P0,RO
Description
Enable the SRAM read/write pointer used as transmit /receive address.
Reserved
PHS0,RW
Enable Link Status Change of port 0 or 1Interrupt
PHS0,RW/C1 Enable Memory Management error interrupt
PHS0,RW
PHS0,RW
PHS0,RW
PHS0,RW
Enable Receive Overflow Counter Overflow Interrupt
Enable Receive Overflow Interrupt
Enable Packet Transmitted Interrupt
Enable Packet Received Interrupt
ROI
PTI
PRI
Preliminarydatasheet
DM9302-15-DS-P01
July 30, 2009
33
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
