DM9302
10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus
1:0
P_PRI
PE0,RW Port Base priority
The priority queue number in port base.
00 : queue 0,
01 : queue 1,
10 : queue 2,
11 : queue 3
6.39 Per Port VLAN Tag Low Byte Register (6EH)
Bit
7:0
Name
VID70
Default
PE01,RW VID[7:0]
Description
Description
6.40 Per Port VLAN Tag High Byte Register (6FH)
Bit
7:5
4
Name
PRI
CFI
Default
PE0,RW Tag [15:13]
PE0,RW Tag[12]
PE0,RW VID[11:8]
3:0
VID118
6.41 MIB Counter Port Index Register (80H)
Bit
7
Name
READY
Default
P0,RO
Description
MIB counter data is ready
When this register is written with INDEX data, this bit is cleared and the MIB
counter reading is in progress. After end of read MIB counter, the MIB data is
loaded into registers 81H~ 84H and this bit is set to indicate that the MIB data is
ready, and then the MIB data of this INDEX is cleared.
6:5
4:0
reserved
INDEX
0,RO
Reserved
PHS0,RW MIB counter index 0~9, each counter is 32-bit in Register 81H~84H.
Write the MIB counter index to this register before read them.
6.42 MIB Counter Data Registers (81H~84H)
Register
81H
82H
83H
84H
Name
Default
X,RO
X,RO
X,RO
X,RO
Description
MIB_DAT
MIB_DAT
MIB_DAT
MIB_DAT
MIB counter Data Register bit 0~7
MIB counter Data Register bit 8~15
MIB counter Data Register bit 16~23
MIB counter Data Register bit 24~31
MIB counter: RX Byte Counter Registers (INDEX 00H)
MIB counter: RX Uni-cast Packet Counter Registers (INDEX 01H)
MIB counter: RX Multi-cast Packet Counter Registers (INDEX 02H)
MIB counter: RX Discard Packet Counter Registers (INDEX 03H)
MIB counter: RX Error Packet Counter Registers (INDEX 04H)
MIB counter: TX Byte Counter Registers (INDEX 05H)
MIB counter: TX Uni-cast Packet Counter Registers (INDEX 06H)
MIB counter: TX Multi-cast Packet Counter Registers (INDEX 07H)
MIB counter: TX Discard Packet Counter Registers (INDEX 08H)
MIB counter: TX Error Packet Counter Registers (INDEX 09H)
28
Preliminary datasheet
DM9302-15-DS-P01
July 30, 2009
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
