DM9161
10/100 Mbps Fast Ethernet Physical Layer TX/FX Single Chip Transceiver
7. Functional Description
The DM9161 performs all PCS (Physical Coding Sublayer),
The DM9161 Fast Ethernet single-chip transceiver,
providing the functionality as specified in IEEE 802.3u,
integrates a complete 100Base-TX module and a complete
10Base-T module. The DM9161 provides a Media
Independent Interface (MII) as defined in the IEEE 802.3u
standard (Clause 22).
PMA (Physical Media Access), TP-PMD (Twisted Pair
Physical Medium Dependent) sublayer, 10Base-T
Encoder/Decoder, and Twisted Pair Media Access Unit
(TPMAU) functions. Figure 1 shows the major functional
blocks implemented in the DM9161.
100Base-TX
Transmitter
100Base-TX
Receiver
10Base-T
Tranceiver
MII Interface
Carrier
Sense
Collision
Detection Negotiation
Auto
MII Serial
Management
Interface
Figure 7-1
7.1 MII Interface
respect to TXCLK. For each TXCLK period, which
TXEN is asserted, TXD(3:0) are accepted for
transmission by the PHY.
The DM 9161 provides a Media Independent Interface (MII)
as defined in the IEEE 802.3u standard (Clause 22).
The purpose of the MII interface is to provide a simple, easy
to implement connection between the MAC Reconciliation
layer and the PHY. The MII is designed to make the
differences between various media transparent to the MAC
sublayer.
The MII consists of a nibble wide receive data bus, a nibble
wide transmit data bus, and control signals to facilitate data
transfers between the PHY and the Reconciliation layer.
•
•
TXCLK (transmit clock) output to the MAC reconciliation
sublayer is a continuous clock that provides the timing
reference for the transfer of the TXEN, TXD, and TXER
signals.
TXEN (transmit enable) input from the MAC
reconciliation sublayer indicates that nibbles are being
presented on the MII for transmission on the physical
medium.
•
TXD (transmit data) is a nibble (4 bits) of data that are
driven by the reconciliation sublayer synchronously with
Final
13
Version: DM9161-DS-F05
September 10, 2008