DM9010
Single Chip Ethernet Controller with General Processor Interface
6.43 Memory Data Read Command without Address Increment Register (F1H)
Bit
7:0
Name
MRCMDX1
Default
X,RO
Description
Read data from RX SRAM. After the read of this command, the read pointer of
internal SRAM is unchanged.
6.44 Memory Data Read Command with Address Increment Register (F2H)
Bit
Name
Default
Description
7:0
MRCMD
X,RO
Read data from RX SRAM. After the read of this command, the read pointer is
increased by 1,2, or 4, depends on the operator mode (8-bit,16-bit and 32-bit
respectively)
6.45 Memory Data Read_address Register (F4H~F5H)
Bit
7:0
7:0
Name
MDRAH
MDRAL
Default
Description
PHS0,RW Memory Data Read_ address High Byte. It will be set to 0Ch, when IMR bit7 =1
PHS0,RW Memory Data Read_ address Low Byte
6.46 Memory Data Write Command without Address Increment Register (F6H)
Bit
7:0
Name
MWCMDX
Default
X,WO
Description
Write data to TX SRAM. After the write of this command, the write pointer is
unchanged
6.47 Memory data write command with address increment Register (F8H)
Bit
Name
Default
Description
7:0
MWCMD
X,WO
Write Data to TX SRAM
After the write of this command, the write pointer is increased by 1,2, or 4, depends
on the operator mode. (8-bit, 16-bit,32-bit respectively)
6.48 Memory data write_address Register (FAH~FBH)
Bit
7:0
7:0
Name
MDRAH
MDRAL
Default
Description
PHS0,RW Memory Data Write_ address High Byte
PHS0,RW Memory Data Write_ address Low Byte
6.49 TX Packet Length Register (FCH~FDH)
Bit
7:0
7:0
Name
TXPLH
TXPLL
Default
Description
Description
PHS0,RW TX Packet Length High byte
PHS0,RW TX Packet Length Low byte
6.50 Interrupt Status Register (FEH)
Bit
Name
Default
Preliminary
28
Version: DM9010-17--DS-P04
Jan. 18, 2006
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
