DM9000A
Ethernet Controller with General Processor Interface
These pins are input ports at default.
5.2 EEPROM Interface
Pin No.
Pin Name
Type
Description
19
20
EEDIO
EECK
I/O,PD IO Data to EEPROM
Clock to EEPROM
O,PD
This pin is also used as the strap pin of the polarity of the INT pin
When this pin is pulled high, the INT pin is low active; otherwise the INT pin is
high active
21
EECS
Chip Select to EEPROM
This pin is also used as a strap pin to define the internal memory data bus
O,PD
width. When it is pulled high, the memory access bus is 8-bit; Otherwise it
is 16-bit.
Type
Description
5.3 Clock Interface
Pin No.
Pin Name
43
44
X2
X1
O
I
Crystal 25MHz Out
Crystal 25MHz In
5.4 LED Interface
Pin No.
Pin Name
Type
Description
39
LED1
O
38
LED2
O
Speed LED
Its low output indicates that the internal PHY is operated in 100M/S, or it
is floating for the 10M mode of the internal PHY.
This pin also acts as ISA bus IO16 defined in EEPROM setting in 16-bit
mode.
Link / Active LED
In LED mode 1, it is the combined LED of link and carrier sense signal of
the internal PHY
In LED mode 0, it is the LED of the carrier sense signal of the internal
PHY only
This pin also acts as ISA bus IOWAIT or WAKE defined in EEPROM
setting in 16-bit mode.
5.5 10/100 PHY/Fiber
Pin No.
Pin Name
Type
Description
46
48
1
2
9
3
Final
SD
BGGND
BGRES
RXVDD25
TXVDD25
RX+
I
P
I/O
P
P
I/O
Fiber-optic Signal Detect
PECL signal, which indicates whether or not the fiber-optic receive pair is
receiving valid levels
Bandgap Ground
Bandgap Pin
2.5V power output for TP RX
2.5V power output for TP TX
TP RX Input
11
Version: DM9000A-17-DS-F01
May 10, 2006
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
