DM562P
V.90 Integrated Data/ Fax/Voice/Speakerphone
Modem Device Single Chip with Memory Built in
7. HDLC Description
0: indicates the data in the TxFIFO has deceased
to zero and the HDLC circuit has transferred the
1st 7eH pattern.
1:indicates that the TxFIFO data is greater than
or equal to the threshold value.
HDLC RxDataBits Register: Address DC00H
Write only
Once the RxDataBit set to 1, the data in the RxBuffer
will be transferred to RxFIFO. The transfer bit
number is the same as the programming value of
RxDataBits Register.
Bit1:Rxdata
0: all the data in the RxBuffer has been read.
1:Programed by software to indicate that all data
in the RxDataBits register has been written to the
RxBuffer.
HDLC RxBuffer: Address DC01H
Write only
Receive data will be written to the RxBuffer and will
be input to the RxHDLC circuit. The RxBuffer is 16
bytes wide.
Bit2:TxFIFO Threshold
0: TxFIFO threshold No. = 11
1: TxFIFO threshold No. =16
HDLC RxFiFo: Address DC01H
Bit3:TxFiFo Status
Read only
0:data No. in TxFIFO >= threshold
1:data No. in TxFIFO <= threshold
After the data has been passed from the RxBuffer to
the RxHDLC circuit, the RxHDLC circuit will remove
the 7eH patterns and transfer the results to the
RxFIFO. There RxFIFO is 21 bytes wide.
Bit4:Txdata
0:A write action to TxDataBites register will clear
this bit.
HDLC TxDataBits Register: Address DC02H
1:Bit No. in TxBuffer = TxDataBits register.
Write only
Bit5: RxFIFO empty
Data written to TxDataBits will be presented to the
TxFIFO. The data in TxFIFO will be transferred to
TXHDLC circuit. The transfer bit number is the same
as the value of TxDataBits register. If the TxFIFO is
empty , a 7e pattern will be loaded to the TxFIFO. If
TxFIFO is not empty and the data frame has the
pattern of five consecutive “1” , then the TXHDLC
circuit will insert “0” automatically.
0:data bytes No. in RxFIFO <>0
1:data bytes No. in RxFIFO = 0
Bit6: Reset
0:Normal state
1:reset HDLC circuit
Zero Deletion In _ buffer register: Address
DC08H
HDLC TxFiFo Register: Address DC03H
write only
Write only
Controller write the original data to this temp buffer.
The original HDLC frame data will be loaded to the
TxFIFO, presented to the input of the TxHDLC circuit.
The TxFIFO is 21 bytes wide.
Zero Deletion Out _ buffer register: Address
DC08H
read only
HDLC TxBuffer: Address DC03H
Controller read the result data from this buffer
Read only
Zero Deletion Status/Rst register: Address DC09H
Bit0: data ready flag (read only)
1:data has been load to out _ buffer. (clear
automatically by a read from out_ buffer)
0: data has not been load to out _ buffer.
Bit1: frame end flag (read only)
According to TxDataBits, the TxHDLC circuit will
transfer the same number data bits to the TxBuffer.
The TxBuffer is 16 bytes wide.
HDLC CNTL/STATUS Register: Address DC04H
Bit0:TxReady0
16
Final
Version: DM562P-DS-F01
February 02, 2004
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
