Extremely Accurate I
2
C-Integrated
RTC/TCXO/Crystal
DS3231
Data Transfer on I
2
C Serial Bus
SDA
t
BUF
t
LOW
t
R
t
F
t
HD:STA
t
SP
SCL
t
HD:STA
STOP
START
t
HD:DAT
t
HIGH
t
SU:DAT
REPEATED
START
t
SU:STA
t
SU:STO
Limits at -40°C are guaranteed by design and not production tested.
All voltages are referenced to ground.
I
CCA
—SCL clocking at max frequency = 400kHz.
Current is the averaged input current, which includes the temperature conversion current.
The
RST
pin has an internal 50kΩ (nominal) pullup resistor to V
CC
.
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IH(MIN)
of the SCL signal)
to bridge the undefined region of the falling edge of SCL.
Note 8:
The maximum t
HD:DAT
needs only to be met if the device does not stretch the low period (t
LOW
) of the SCL signal.
Note 9:
A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
≥
250ns must then be met. This
is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the
low period of the SCL signal, it must output the next data bit to the SDA line t
R(MAX)
+ t
SU:DAT
= 1000 + 250 = 1250ns
before the SCL line is released.
Note 10:
C
B
—total capacitance of one bus line in pF.
Note 11:
The parameter t
OSF
is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of
0.0V
≤
V
CC
≤
V
CC(MAX)
and 2.3V
≤
V
BAT
≤
3.4V.
Note 12:
This delay applies only if the oscillator is enabled and running. If the
EOSC
bit is a 1, the startup time of the oscillator is
added to this delay.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
6
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