欢迎访问ic37.com |
会员登录 免费注册
发布采购

DS2175 参数 Datasheet PDF下载

DS2175图片预览
型号: DS2175
PDF下载: 下载PDF文件 查看货源
内容描述: T1 / CEPT弹性商店 [T1/CEPT Elastic Store]
分类和应用:
文件页数/大小: 12 页 / 246 K
品牌: DALLAS [ DALLAS SEMICONDUCTOR ]
 浏览型号DS2175的Datasheet PDF文件第1页浏览型号DS2175的Datasheet PDF文件第2页浏览型号DS2175的Datasheet PDF文件第4页浏览型号DS2175的Datasheet PDF文件第5页浏览型号DS2175的Datasheet PDF文件第6页浏览型号DS2175的Datasheet PDF文件第7页浏览型号DS2175的Datasheet PDF文件第8页浏览型号DS2175的Datasheet PDF文件第9页  
DS2175  
PIN Description Table 1  
DESCRIPTION  
PIN  
SYMBOL  
TYPE  
1
RCLKSEL  
I
Receive Clock Select. Tie to VSS for 1.544 MHz applications, to  
VDD for 2.048 MHz.  
2
3
4
RCLK  
RSER  
RMSYNC  
I
I
I
Receive Clock. 1.544 or 2.048 MHz data clock.  
Receive Serial Data. Sampled on falling edge of RCLK.  
Receive Multifram Sync. Rising edge establishes receive side  
frame and multiframe boundaries.  
5
6
7
FSD  
O
O
I
Frame Slip Directions. State indicates direction of last slip;  
latched on slip occurrence.  
Frame Slip. Active low, open collector output. Held low for 65  
SYSCLK cycles when a slip occurs.  
Align. Recenters buffer on next system side frame boundary when  
forced low; negative edge-triggered.  
SLIP  
ALN  
8
9
VSS  
SCLKSEL  
I
Signal Ground. 0.0 volts.  
System Clock Select. Tie to VSS for 1.544 MHz applications, to  
VDD for 2.048 MHz.  
10  
11  
12  
13  
I
O
I
Serial/Parallel Select. Tie to VSS for parallel backplane  
applications, to VDD for serial.  
System Channel Clock. Transitions high on channel boundaries;  
useful for serial to parallel conversion of channel data.  
System Frame Sync. Rising edge establishes system side frame  
boundaries.  
System Multiframe Sync. Slip-compensated multiframe output;  
used with RMSYNC to monitor depth of store real time.  
System Serial Data. Updated on rising edge of SYSCLK.  
System Clock. 1.544 or 2.048 MHz data clock.  
Positive Supply. 5.0 volts.  
S/P  
SCHCLK  
SFSYNC  
SMSYNC  
O
14  
15  
16  
SSER  
SYSCLK  
VDD  
O
I
PCM BUFFER  
The DS2175 utilizes a 2–frame buffer to synchronize in-coming PCM data to the system backplane clock.  
Buffer depth is mode–dependent; 2.048 MHz to 2.048 MHz applications utilize 64 bytes of buffer  
memory, while all other modes are supported by 48 bytes. The buffer samples data at RSER on the falling  
edge of RCLK. Output data appears at SSER and is updated on the rising edge of SYSCLK. The buffer  
depth is constantly monitored by onboard contention logic; a “slip” occurs when the buffer is completely  
emptied or filled. Slips automatically recenter the buffer to a one–frame depth and always occur on frame  
boundaries.  
DATA FORMAT  
Data is presented to, and output from, the elastic store in a “framed” format. A rising edge at RMSYNC  
and SFSYNC establishes frame boundaries for the receive and system sides. North American (T1) frames  
contain 24 data channels of 8 bits each and an F–bit (193 bits total). European (CEPT) frames contain 32  
data channels (256 bits). The frame rate of both systems is 8 KHz. RMSYNC and SFSYNC do not  
require a pulse at every frame boundary; if desired, they may be pulsed once to establish frame alignment.  
Internal counters will then maintain the frame alignment and may be reinforced by the next rising edge at  
RMSYNC and/or SFSYNC.  
3 of 12