DS2154
1.0 INTRODUCTION
The DS2154 is a super-set version of the popular DS2153 E1 Single-Chip Transceiver offering the new
features listed below. All of the original features of the DS2153 have been retained and software created
for the original devices is transferable into the DS2154.
NEW FEATURES
Option for non-multiplexed bus operation
SECTION
1 and 2
12
Crystal-less jitter attenuation
Additional hardware signaling capability including:
Receive signaling reinsertion to a backplane multiframe sync
Availability of signaling in a separate PCM data stream
Signaling freezing
7
Interrupt generated on change of signaling data
Improved receive sensitivity: 0 dB to -43 dB
12
8
Per-channel code insertion in both transmit and receive paths
Expanded access to Sa and Si bits
11
4
RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state
8.192 MHz clock synthesizer
1
Per-channel loopback
8
Addition of hardware pins to indicate carrier loss and signaling freeze
1
Line interface function can be completely decoupled from the framer/formatter to
allow:
Interface to optical, HDSL, and other NRZ interfaces
1
“tap” the transmit and receive bipolar data streams for monitoring purposes
Be able corrupt data and insert framing errors, CRC errors, etc.
Transmit and receive elastic stores now have independent backplane clocks
1
Ability to monitor one DS0 channel in both the transmit and receive paths
Access to the data streams in between the framer/formatter and the elastic stores
AIS generation in the line interface that is independent of loopbacks
Transmit current limiter to meet the 50 mA short circuit requirement
Option to extend carrier loss criteria to a 1 ms period as per ETS 300 233
Automatic RAI generation to ETS 300 011 specifications
6
1
1 and 3
12
3
3
4 of 87
DALLAS [ DALLAS SEMICONDUCTOR ]
