欢迎访问ic37.com |
会员登录 免费注册
发布采购

DS2154LN 参数 Datasheet PDF下载

DS2154LN图片预览
型号: DS2154LN
PDF下载: 下载PDF文件 查看货源
内容描述: 增强型E1单芯片收发器 [Enhanced E1 Single Chip Transceiver]
分类和应用: 数字传输控制器电信集成电路电信电路PC
文件页数/大小: 87 页 / 1103 K
品牌: DALLAS [ DALLAS SEMICONDUCTOR ]
 浏览型号DS2154LN的Datasheet PDF文件第8页浏览型号DS2154LN的Datasheet PDF文件第9页浏览型号DS2154LN的Datasheet PDF文件第10页浏览型号DS2154LN的Datasheet PDF文件第11页浏览型号DS2154LN的Datasheet PDF文件第13页浏览型号DS2154LN的Datasheet PDF文件第14页浏览型号DS2154LN的Datasheet PDF文件第15页浏览型号DS2154LN的Datasheet PDF文件第16页  
DS2154  
Receive Sync [RSYNC]. An extracted pulse, one RCLK wide, is output at this pin which identifies either  
frame or CAS/CRC multiframe boundaries. If the receive side elastic store is enabled, then this pin can be  
enabled to be an input at which a frame or multiframe boundary pulse synchronous with RSYSCLK is  
applied.  
Receive Frame Sync [RFSYNC]. An extracted 8 kHz pulse, one RCLK wide, is output at this pin which  
identifies frame boundaries.  
Receive Multiframe Sync [RMSYNC]. An extracted pulse, one RSYSCLK wide, is output at this pin  
which identifies multiframe boundaries. If the receive side elastic store is disabled, then this output will  
output multiframe boundaries associated with RCLK.  
Receive Data [RDATA]. Updated on the rising edge of RCLK with the data out of the receive side  
framer.  
Receive System Clock [RSYSCLK]. 1.544 MHz or 2.048 MHz clock. Only used when the elastic store  
function is enabled. Should be tied low in applications that do not use the elastic store. Can be burst at  
rates up to 8.192 MHz.  
Receive Signaling Output [RSIG]. Outputs signaling bits in a PCM format. Updated on rising edges of  
RCLK when the receive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the  
receive side elastic store is enabled. See Section 13 for timing examples.  
Receive Loss of Sync / Loss of Transmit Clock [RLOS/LOTC]. A dual function output that is  
controlled by the TCR2.0 control bit. This pin can be programmed to either toggle high when the  
synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not been  
toggled for 5 µs.  
Receive Carrier Loss [RCL]. Set high when the line interface detects a loss of carrier. [Note: a test  
mode exists to allow the DS2154 to detect carrier loss at RPOSI and RNEGI in place of detection at RTIP  
and RRING].  
Receive Signaling Freeze [RSIGF]. Set high when the signaling data is frozen via either automatic or  
manual intervention. Used to alert downstream equipment of the condition.  
8 MHz Clock [8MCLK]. 8.192 MHz output clock that is referenced to the clock that is output at the  
RCLK pin.  
Receive Positive Data Output [RPOSO]. Updated on the rising edge of RCLKO with the bipolar data  
out of the line interface. This pin is normally tied to RPOSI.  
Receive Negative Data Output [RNEGO]. Updated on the rising edge of RCLKO with the bipolar data  
out of the line interface. This pin is normally tied to RNEGI.  
Receive Clock Output [RCLKO]. Buffered recovered clock from the E1 line. This pin is normally tied  
to RCLKI.  
Receive Positive Data Input [RPOSI]. Sampled on the falling edge of RCLKI for data to be clocked  
through the receive side framer. RPOSI and RNEGI can be tied together for a NRZ interface. Can be  
internally connected to RPOSO by tying the LIUC pin high.  
12 of 87