DS18B20
data from the DS18B20 is valid for 15μs after the falling edge that initiated the read time slot. Therefore,
the master must release the bus and then sample the bus state within 15μs from the start of the slot.
Figure 15 illustrates that the sum of TINIT, TRC, and TSAMPLE must be less than 15μs for a read time slot.
Figure 16 shows that system timing margin is maximized by keeping TINIT and TRC as short as possible
and by locating the master sample time during read time slots towards the end of the 15μs period.
Figure 15. Detailed Master Read 1 Timing
VPU
VIH of Master
1-WIRE BUS
GND
Master samples
TINT > 1μs
TRC
15μs
Figure 16. Recommended Master Read 1 Timing
VPU
VIH of Master
1-WIRE BUS
GND
Master samples
TINT
= TRC =
small small
15μs
LINE TYPE LEGEND
Bus master pulling low
Resistor pullup
RELATED APPLICATION NOTES
The following application notes can be applied to the DS18B20 and are available on our website at
www.maxim-ic.com.
Application Note 27: Understanding and Using Cyclic Redundancy Checks with Maxim iButton Products
Application Note 122: Using Dallas' 1-Wire ICs in 1-Cell Li-Ion Battery Packs with Low-Side N-Channel
Safety FETs Master
Application Note 126: 1-Wire Communication Through Software
Application Note 162: Interfacing the DS18x20/DS1822 1-Wire Temperature Sensor in a Microcontroller
Environment
Application Note 208: Curve Fitting the Error of a Bandgap-Based Digital Temperature Sensor
Application Note 2420: 1-Wire Communication with a Microchip PICmicro Microcontroller
Application Note 3754: Single-Wire Serial Bus Carries Isolated Power and Data
Sample 1-Wire subroutines that can be used in conjunction with Application Note 74: Reading and
Writing iButtons via Serial Interfaces can be downloaded from the Maxim website.
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DALLAS [ DALLAS SEMICONDUCTOR ]
