DS1820
64–BIT LASERED ROM
Each DS1820 contains a unique ROM code that is
64–bits long. The first eight bits are a 1–Wire family
code (DS1820 code is 10h). The next 48 bits are a
unique serial number. The last eight bits are a CRC of
the first 56 bits. (See Figure 5.) The 64–bit ROM and
ROM Function Control section allow the DS1820 to
operate as a 1–Wire device and follow the 1–Wire proto-
col detailed in the section “1–Wire Bus System”. The
functions required to control sections of the DS1820 are
not accessible until the ROM function protocol has been
satisfied. This protocol is described in the ROM function
protocol flowchart (Figure 6). The 1–Wire bus master
must first provide one of five ROM function commands:
1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip
ROM, or 5) Alarm Search. After a ROM functions
sequence has been successfully executed, the func-
tions specific to the DS1820 are accessible and the bus
master may then provide and one of the six memory and
control function commands.
vides this value to the bus master to validate the transfer
of data bytes. In each case where a CRC is used for data
transfer validation, the bus master must calculate a
CRC value using the polynomial function given above
and compare the calculated value to either the 8–bit
CRC value stored in the 64–bit ROM portion of the
DS1820 (for ROM reads) or the 8–bit CRC value com-
puted within the DS1820 (which is read as a ninth byte
when the scratchpad is read). The comparison of CRC
values and decision to continue with an operation are
determined entirely by the bus master. There is no cir-
cuitry inside the DS1820 that prevents a command
sequence from proceeding if the CRC stored in or calcu-
lated by the DS1820 does not match the value gener-
ated by the bus master.
The 1–Wire CRC can be generated using a polynomial
generator consisting of a shift register and XOR gates
as shown in Figure 7. Additional information about the
Dallas 1–Wire Cyclic Redundancy Check is available in
Application Note 27 entitled “Understanding and Using
Cyclic Redundancy Checks with Dallas Semiconductor
Touch Memory Products”.
The shift register bits are initialized to zero. Then start-
ing with the least significant bit of the family code, one bit
at a time is shifted in. After the 8th bit of the family code
has been entered, then the serial number is entered.
After the 48th bit of the serial number has been entered,
the shift register contains the CRC value. Shifting in the
eight bits of CRC should return the shift register to all
zeros.
CRC GENERATION
The DS1820 has an 8–bit CRC stored in the most signif-
icant byte of the 64–bit ROM. The bus master can com-
pute a CRC value from the first 56–bits of the 64–bit
ROM and compare it to the value stored within the
DS1820 to determine if the ROM data has been
received error–free by the bus master. The equivalent
polynomial function of this CRC is:
CRC = X
8
+ X
5
+ X
4
+ 1
The DS1820 also generates an 8–bit CRC value using
the same polynomial function shown above and pro-
64–BIT LASERED ROM
Figure 5
8–BIT CRC CODE
MSB
LSB
48–BIT SERIAL NUMBER
MSB
LSB
8–BIT FAMILY CODE (10h)
MSB
LSB
030598 6/27
DALLAS [ DALLAS SEMICONDUCTOR ]
