DS1621
NOTES:
1. All voltages are referenced to ground.
2. I/O pins of fast mode devices must not obstruct the SDA and SCL lines if VDD is switched off.
3. ICC specified with TOUT pin open.
4. ICC specified with VCC at 5.0V and SDA, SCL = 5.0V, 0°C to 70°C.
5. After this period, the first clock pulse is generated.
6. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the
VIH MIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
7. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the
SCL signal.
8. A fast mode device can be used in a standard mode system, but the requirement tSU:DAT >250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line tRMAX+tSU:DAT = 1000+250 = 1250 ns before the SCL line is released.
9. Cb – total capacitance of one bus line in pF.
10. Writing to the nonvolatile memory should only take place in the 0°C to 70°C temperature range.
11. See typical curve for specification limits outside 0°C to 70°C range. Thermometer error reflects
sensor accuracy as tested during calibration.
TIMING DIAGRAM
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102299
DALLAS [ DALLAS SEMICONDUCTOR ]
