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DS1339U-33+ 参数 Datasheet PDF下载

DS1339U-33+图片预览
型号: DS1339U-33+
PDF下载: 下载PDF文件 查看货源
内容描述: I²C串行实时时钟 [I2C Serial Real-Time Clock]
分类和应用: 外围集成电路光电二极管时钟
文件页数/大小: 18 页 / 280 K
品牌: DALLAS [ DALLAS SEMICONDUCTOR ]
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DS1339 I2C Serial Real-Time Clock  
POWER-UP/DOWN CHARACTERISTICS  
(TA = -40 C to +85°C) (Note 1, Figure 1)  
PARAMETER  
Recovery at Power-Up  
SYMBOL  
tREC  
CONDITIONS  
(Note 14)  
MIN  
TYP  
MAX  
2
UNITS  
ms  
VCC Fall Time; VPF(MAX) to VPF(MIN)  
VCC Rise Time; VPF(MIN) to VPF(MAX)  
tVCCF  
300  
0
s  
tVCCR  
s  
WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in  
battery-backup mode.  
Note 1:  
Note 2:  
Note 3:  
Note 4:  
Note 5:  
Note 6:  
Note 7:  
Note 8:  
Limits at -40°C are guaranteed by design and are not production tested.  
SCL only.  
SDA and SQW/INT.  
ICCA—SCL at fSC max, VIL = 0.0V, VIH = VCC, trickle charger disabled.  
Specified with the I2C bus inactive, VIL = 0.0V, VIH = VCC, trickle charger disabled.  
Using recommended crystal on X1 and X2.  
After this period, the first clock pulse is generated.  
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge  
the undefined region of the falling edge of SCL.  
Note 9:  
The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal.  
Note 10:  
A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT O to 250ns must then be met. This is  
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW  
period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line  
is released.  
Note 11:  
Note 12:  
Note 13:  
CB—total capacitance of one bus line in pF.  
Guaranteed by design. Not production tested.  
The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of 0.0V ?  
VCC ? VCCMAX and 1.3V ? VBACKUP ? 3.7V.  
Note 14:  
This delay applies only if the oscillator is running. If the oscillator is disabled or stopped, no power-up delay occurs.  
Figure 1. Power-Up/Down Timing  
VCC  
VPF(MAX)  
VPF(MIN)  
tVCCR  
tVCCF  
tREC  
INPUTS  
RECOGNIZED  
VALID  
RECOGNIZED  
DON'T CARE  
HIGH-Z  
OUTPUTS  
VALID  
5 of 18  
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