欢迎访问ic37.com |
会员登录 免费注册
发布采购

DS1308N 参数 Datasheet PDF下载

DS1308N图片预览
型号: DS1308N
PDF下载: 下载PDF文件 查看货源
内容描述: 64 ×8串行实时时钟 [64 X 8 Serial Real Time Clock]
分类和应用: 外围集成电路时钟
文件页数/大小: 14 页 / 225 K
品牌: DALLAS [ DALLAS SEMICONDUCTOR ]
 浏览型号DS1308N的Datasheet PDF文件第1页浏览型号DS1308N的Datasheet PDF文件第2页浏览型号DS1308N的Datasheet PDF文件第3页浏览型号DS1308N的Datasheet PDF文件第4页浏览型号DS1308N的Datasheet PDF文件第6页浏览型号DS1308N的Datasheet PDF文件第7页浏览型号DS1308N的Datasheet PDF文件第8页浏览型号DS1308N的Datasheet PDF文件第9页  
DS1307/1308  
CONTROL REGISTER  
The DS1307/DS1308 Control Register is used to control the operation of the SQW/OUT pin.  
BIT 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
BIT 0  
OUT  
X
X
SQWE  
X
X
RS1  
RS0  
OUT (Output control): This bit controls the output level of the SQW/OUT pin when the square wave  
output is disabled. If SQWE=0, the logic level on the SQW/OUT pin is 1 if OUT=1 and is 0 if OUT=0.  
SQWE (Square Wave Enable): This bit, when set to a logic 1, will enable the oscillator output. The  
frequency of the square wave output depends upon the value of the RS0 and RS1 bits.  
RS (Rate Select): These bits control the frequency of the square wave output when the square wave  
output has been enabled. Table 1 lists the square wave frequencies that can be selected with the RS bits.  
SQUAREWAVE OUTPUT FREQUENCY Table 1  
RS1  
RS0  
SQW OUTPUT  
FREQUENCY  
1 Hz  
0
0
1
1
0
1
0
1
4.096 kHz  
8.192 kHz  
32.768 kHz  
2-WIRE SERIAL DATA BUS  
The DS1307 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends  
data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that  
controls the message is called a master. The devices that are controlled by the master are referred to as  
slaves. The bus must be controlled by a master device which generates the serial clock (SCL), controls  
the bus access, and generates the START and STOP conditions. The DS1307/DS1308 operates as a slave  
on the 2-wire bus. A typical bus configuration using this 2-wire protocol is show in Figure 4.  
TYPICAL 2-WIRE BUS CONFIGURATION Figure 4  
5 of 14  
 复制成功!