DS1307/1308
AC ELECTRICAL CHARACTERISTICS
(0°C to 70°C or -40°C to +85°C; VCC =4.5V to 5.5V)
PARAMETER
SYMBOL MIN
TYP
MAX
UNITS NOTES
SCL Clock Frequency
Bus Free Time Between a STOP and
START Condition
fSCL
tBUF
0
4.7
100
kHz
µs
Hold Time (Repeated) START Condition
LOW Period of SCL Clock
HIGH Period of SCL Clock
Set-up Time for a Repeated START
Condition
tHD:STA
tLOW
tHIGH
4.0
4.7
4.0
4.7
5
6, 7
8
µs
µs
µs
µs
tSU:STA
Data Hold Time
Data Set-up Time
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
CB
0
250
µs
ns
ns
ns
µs
pF
pF
pF
Rise Time of Both SDA and SCL Signals
Fall Time of Both SDA and SCL Signals
Set-up Time for STOP Condition
Capacitive Load for each Bus Line
I/O Capacitance
1000
300
4.7
400
CI/O
10
12.5
Crystal Specified Load Capacitance
NOTES:
1. All voltages are referenced to ground.
2. Logic zero voltages are specified at a sink current of 5 mA at VCC=4.5V, VOL=GND for capacitive
loads.
3. ICCS specified with VCC=5.0V and SDA, SCL=5.0V.
4. VCC=0V, VBAT=3V.
5. After this period, the first clock pulse is generated.
6. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the
VIHMIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
7. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the
SCL signal.
8. CB - total capacitance of one bus line in pF.
9.
ICCA - SCL clocking at max frequency = 100 kHz.
10. SCL only.
11. SDA and SQW/OUT
12. The DS1308 is designed to be subjected to no more than two passes through a solder reflow process
to limit premature crystal aging effects and maintain a reasonable accuracy of ±2 minutes/month at
25 degrees C (worst case).
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DALLAS [ DALLAS SEMICONDUCTOR ]
