DS1307/1308
Depending upon the state of the R/
W
bit, two types of data transfer are possible:
1.
Data transfer from a master transmitter to a slave receiver.
The first byte transmitted by the
master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge
bit after each received byte. Data is transferred with the most significant bit (MSB) first.
2.
Data transfer from a slave transmitter to a master receiver.
The first byte (the slave address) is
transmitted by the master. The slave then returns an acknowledge bit. This is followed by the slave
transmitting a number of data bytes. The master returns an acknowledge bit after all received bytes
other than the last byte. At the end of the last received byte, a ’not acknowledge’ is returned.
The master device generates all of the serial clock pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the bus will not be released. Data is transferred
with the most significant bit (MSB) first.
The DS1307/DS1308 may operate in the following two modes:
1.
Slave receiver mode (DS1307/DS1308 write mode):
Serial data and clock are received through
SDA and SCL. After each byte is received an acknowledge bit is transmitted. START and STOP
conditions are recognized as the beginning and end of a serial transfer. Address recognition is
performed by hardware after reception of the slave address and *direction bit (See Figure 6). The
address byte is the first byte received after the start condition is generated by the master. The address
byte contains the 7 bit DS1307/DS1308 address, which is 1101000, followed by the *direction bit
(R/
W
) which, for a write, is a 0. After receiving and decoding the address byte the device outputs an
acknowledge on the SDA line. After the DS1307/DS1308 acknowledges the slave address + write
bit, the master transmits a register address to the DS1307/DS1308 This will set the register pointer on
the DS1307/DS1308. The master will then begin transmitting each byte of data with the
DS1307/DS1308 acknowledging each byte received. The master will generate a stop condition to
terminate the data write.
DATA WRITE - SLAVE RECEIVER MODE
Figure 6
2.
Slave transmitter mode (DS1307/DS1308 read mode):
The first byte is received and handled as in
the slave receiver mode. However, in this mode, the *direction bit will indicate that the transfer
direction is reversed. Serial data is transmitted on SDA by the DS1307/DS1308 while the serial clock
is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial
transfer (See Figure 7). The address byte is the first byte received after the start condition is
generated by the master. The address byte contains the 7-bit DS1307/DS1308 address, which is
1101000, followed by the *direction bit (R/
W
) which, for a read, is a 1. After receiving and
decoding the address byte the device inputs an acknowledge on the SDA line. The DS1307/DS1308
then begins to transmit data starting with the register address pointed to by the register pointer. If the
register pointer is not written to before the initiation of a read mode the first address that is read is the
last one stored in the register pointer. The DS1307/DS1308 must receive a Not Acknowledge to end
a read.
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DALLAS [ DALLAS SEMICONDUCTOR ]
