DS1302 Trickle-Charge Timekeeping Chip
The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but
must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on.). Illogical time and date entries
result in undefined operation.
When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the
internal registers update. When reading the time and date registers, the user buffers are synchronized to the
internal registers the rising edge of CE.
The countdown chain is reset whenever the seconds register is written. Write transfers occur on the falling edge of
CE. To avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be
written within 1 second.
The DS1302 can be run in either 12-hour or 24-hour mode. Bit 7 of the hours register is defined as the 12- or 24-
hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the
AM/
PM bit with
logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20–23 hours). The hours data must be
re-initialized whenever the 12/
24
bit is changed.
CLOCK HALT FLAG
Bit 7 of the seconds register is defined as the clock halt (CH) flag. When this bit is set to logic 1, the clock oscillator
is stopped and the DS1302 is placed into a low-power standby mode with a current drain of less than 100nA. When
this bit is written to logic 0, the clock will start. The initial power-on state is not defined.
WRITE-PROTECT BIT
Bit 7 of the control register is the write-protect bit. The first seven bits (bits 0 to 6) are forced to 0 and always read 0
when read. Before any write operation to the clock or RAM, bit 7 must be 0. When high, the write-protect bit
prevents a write operation to any other register. The initial power-on state is not defined. Therefore, the WP bit
should be cleared before attempting to write to the device.
TRICKLE-CHARGE REGISTER
This register controls the trickle-charge characteristics of the DS1302. The simplified schematic of Figure 6 shows
the basic components of the trickle charger. The trickle-charge select (TCS) bits (bits 4 to 7) control the selection of
the trickle charger. To prevent accidental enabling, only a pattern of 1010 enables the trickle charger. All other
patterns will disable the trickle charger. The DS1302 powers up with the trickle charger disabled. The diode select
(DS) bits (bits 2 and 3) select whether one diode or two diodes are connected between V
CC2
and V
CC1
. If DS is 01,
one diode is selected or if DS is 10, two diodes are selected. If DS is 00 or 11, the trickle charger is disabled
independently of TCS. The RS bits (bits 0 and 1) select the resistor that is connected between V
CC2
and V
CC1
. The
resistor selected by the resistor select (RS) bits is as follows:
RS BITS
00
01
10
11
RESISTOR
None
R1
R2
R3
TYPICAL
VALUE
None
2kΩ
4kΩ
8kΩ
If RS is 00, the trickle charger is disabled independently of TCS.
Diode and resistor selection is determined by the user according to the maximum current desired for battery or
super cap charging. The maximum charging current can be calculated as illustrated in the following example.
Assume that a system power supply of 5V is applied to V
CC2
and a super cap is connected to V
CC1
. Also assume
that the trickle charger has been enabled with one diode and resistor R1 between V
CC2
and V
CC1
. The maximum
current I
MAX
would therefore be calculated as follows:
I
MAX
= (5.0V – diode drop) / R1
≈
(5.0V – 0.7V) / 2kΩ
≈
2.2mA
As the super cap charges, the voltage drop between V
CC2
and V
CC1
decreases and therefore the charge current
decreases.
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DALLAS [ DALLAS SEMICONDUCTOR ]
