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DS1284Q 参数 Datasheet PDF下载

DS1284Q图片预览
型号: DS1284Q
PDF下载: 下载PDF文件 查看货源
内容描述: 看门狗计时器 [Watchdog Timekeepers]
分类和应用: 计时器或实时时钟微控制器和处理器外围集成电路双倍数据速率
文件页数/大小: 18 页 / 384 K
品牌: DALLAS [ DALLAS SEMICONDUCTOR ]
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DS1284/DS1286  
TIME-OF-DAY REGISTERS  
Registers 0, 1, 2, 4, 6, 8, 9, and A contain time-of-day data in BCD. Ten bits within these eight registers  
are not used and always read 0 regardless of how they are written. Bits 6 and 7 in the months register (9)  
are binary bits. When set to logic 0, EOSC (bit 7) enables the RTC oscillator. This bit is set to logic 1 as  
shipped from Dallas Semiconductor to prevent lithium energy consumption during storage and shipment.  
The user normally turns this bit on during device initialization. However, the oscillator can be turned on  
and off as necessary by setting this bit to the appropriate level. Bit 6 of this same byte controls the square-  
wave output (pin 23). When set to logic 0, the square-wave output pin outputs a 1024Hz square-wave  
signal. When set to logic 1, the square-wave output pin is in a high-impedance state. Bit 6 of the hours  
register is defined as the 12- or 24-hour select bit. When set to logic 1, the 12-hour format is selected. In  
the 12-hour format, bit 5 is the AM/PM bit with logic 1 being PM. In the 24-hour mode, bit 5 is the  
second 10-hour bit (20–23 hours). The time-of-day registers are updated every 0.01 seconds from the  
RTC, except when the TE bit (bit 7 of register B) is set low or the clock oscillator is not running. The  
preferred method of synchronizing data access to and from the watchdog timekeeper is to access the  
command register by doing a write cycle to address location 0B and setting the TE (transfer enable) bit to  
a logic 0. Doing so freezes the external time-of-day registers at the present recorded time, allowing access  
to occur without danger of simultaneous update. When the watch registers have been read or written, a  
second write cycle to location 0B, setting the TE bit to a logic 1, puts the time-of-day registers back to  
being updated every 0.01 second. No time is lost in the RTC because the internal copy of the time-of-day  
register buffers is continually incremented while the external memory registers are frozen.  
An alternate method of reading and writing the time-of-day registers is to ignore synchronization.  
However, any single read may give erroneous data as the RTC may be in the process of updating the  
external memory registers as data is being read. The internal copies of seconds through years are  
incremented and time-of-day alarm is checked during the period that hundreds of seconds read 99 and are  
transferred to the external register when hundredths of seconds roll from 99 to 00. A way of making sure  
data is valid is to do multiple reads and compare. Writing the registers can also produce erroneous results  
for the same reasons. A way of making sure that the write cycle has caused proper update is to do read  
verifies and re-execute the write cycle if data is not correct. While the possibility of erroneous results  
from reads and write cycles has been stated, it is worth noting that the probability of an incorrect result is  
kept to a minimum due to the redundant structure of the watchdog timekeeper.  
TIME-OF-DAY ALARM REGISTERS  
Registers 3, 5, and 7 contain the time-of-day alarm registers. Bits 3, 4, 5, and 6 of register 7 always read 0  
regardless of how they are written. Bit 7 of registers 3, 5, and 7 are mask bits (Figure 3). When all the  
mask bits are logic 0, a time-of-day alarm only occurs when registers 2, 4, and 6 match the values stored  
in registers 3, 5, and 7. An alarm is generated every day when bit 7 of register 7 is set to logic 1.  
Similarly, an alarm is generated every hour when bit 7 of registers 7 and 5 is set to logic 1. When bit 7 of  
registers 7, 5, and 3 is set to logic 1, an alarm occurs every minute when register 1 (seconds) rolls from 59  
to 00.  
Time-of-day alarm registers are written and read in the same format as the time-of-day registers. The  
time-of-day alarm flag and interrupt is always cleared when alarm registers are read or written.  
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