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DS1225Y-150IND+ 参数 Datasheet PDF下载

DS1225Y-150IND+图片预览
型号: DS1225Y-150IND+
PDF下载: 下载PDF文件 查看货源
内容描述: [Non-Volatile SRAM Module, 2KX8, 150ns, CMOS, PDIP28, DIP-28]
分类和应用: 静态存储器光电二极管内存集成电路
文件页数/大小: 8 页 / 179 K
品牌: DALLAS [ DALLAS SEMICONDUCTOR ]
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19-5603; Rev 10/10  
NOT RECOMMENDED FOR NEW DESIGNS  
DS1225Y  
64k Nonvolatile SRAM  
www.maxim-ic.com  
FEATURES  
PIN ASSIGNMENT  
. 10 years minimum data retention in the  
absence of external power  
VCC  
WE  
NC  
1
28  
27  
NC  
A12  
A7  
A6  
A5  
2
3
4
26  
25  
. Data is automatically protected during power  
loss  
. Directly replaces 2k x 8 volatile static RAM  
or EEPROM  
. Unlimited write cycles  
. Low-power CMOS  
A8  
A9  
5
6
24  
23  
A11  
OE  
A4  
A3  
A2  
7
8
22  
21  
A10  
CE  
DQ7  
DQ6  
A1  
A0  
9
10  
20  
19  
. JEDEC standard 28-pin DIP package  
. Read and write access times of 150 ns  
. Full ±10% operating range  
. Optional industrial temperature range of  
-40°C to +85°C, designated IND  
DQ0  
11  
12  
18  
17  
DQ1  
DQ2  
GND  
DQ5  
DQ4  
DQ3  
13  
14  
16  
15  
24-Pin ENCAPSULATED PACKAGE  
720-mil EXTENDED  
PIN DESCRIPTION  
A0-A12  
- Address Inputs  
DQ0-DQ7  
- Data In/Data Out  
- Chip Enable  
- Write Enable  
CE  
WE  
- Output Enable  
- Power (+5V)  
- Ground  
OE  
VCC  
GND  
DESCRIPTION  
The DS1225Y 64k Nonvolatile SRAM is a 65,536-bit, fully static, nonvolatile RAM organized as 8192  
words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which  
constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium  
energy source is automatically switched on and write protection is unconditionally enabled to prevent  
data corruption. The NV SRAM can be used in place of existing 8k x 8 SRAMs directly conforming to  
the popular bytewide 28-pin DIP standard. The DS1225Y also matches the pinout of the 2764 EPROM or  
the 2864 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the  
number of write cycles that can be executed and no additional support circuitry is required for micro-  
processor interfacing.  
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