3.3V Spread-Spectrum EconOscillator
DS1087L
Table
1. Register Summary
REGISTER
PRESCALER
ADDR
WRITE EE
ADDR
02h
0Dh
3Fh
X
1
X
1
X
1
X
1
LO/
HIZ
X
1
BINARY
J0
X
1
P3
WC
P2
A2
P1
A1
P0
A0
FACTORY DEFAULT
110- - - - - b
11110000b
—
ACCESS
R/W
R/W
—
No Data
X
1
= Don’t care; read as one.
Detailed Description
A block diagram of the DS1087L is shown in
Figure
1.
Output Frequency
The internal master oscillator can generate a square
wave with a frequency range of 33.3MHz to 66.6MHz.
The master oscillator frequency and output frequency
are factory programmed, although the user can use the
programmable divider to divide the master oscillator
frequency by 2
x
(where x equals 0 to 8).
Output Control and Power-Down
Two user control signals control the output. The output-
enable pin, OE, gates the clock output buffer and the
PDN
pin disables the master oscillator and turns off the
output for power-sensitive applications (note: the
power-down command must persist for at least two out-
put frequency cycles plus 10µs for deglitching purpos-
es). On power-up, the output is disabled until power is
stable and the master oscillator has generated 512
clock cycles.
Both controls feature a synchronous enable, which
ensures there are no output glitches when the output is
enabled. The synchronous enable also ensures a con-
stant time interval (for a given frequency setting) from
an enable signal to the first output transition.
programmed frequency. Although the output frequency
changes when the dither is enabled, the duty cycle
does not change.
The dither is controlled by the J0 bit in the PRESCALER
register and enabled with the SPRD pin. The maximum
spectral attenuation occurs when the prescaler is set to
1. The spectral attenuation is reduced by 2.7dB for
every factor of 2 that is used in the prescaler. This hap-
pens because the prescaler’s divider function tends to
average the dither in creating the lower frequency.
However, the most stringent spectral emission limits are
imposed on the higher frequencies where the prescaler
is set to a low divider ratio.
A triangle-wave generator injects an offset element into
the master oscillator to dither its output. The dither rate
(see Equation 1) is based on the master oscillator fre-
quency.
Figure
2 shows a plot of the output frequency
versus dither rate.
Dither Rate
=
f
0
4096
(1)
where f
0
= master oscillator frequency
Register Summary
The DS1087L registers are used to change the dither
amount, output frequency, and slave address. A sum-
mary of the registers is shown in
Table
1. Once pro-
grammed into EEPROM, the settings only need to be
reprogrammed if it is desired to reconfigure the device.
Spread Spectrum
The DS1087L can reduce radiated emission peaks. The
output frequency can be dithered 2% or 4% below the
OUTPUT FREQUENCY
PRESCALER Register
Bit 5:
Output Low or High-Z.
The LO/HIZ bit
controls the output. During power-down,
while the output is deactivated, if the
LO/HIZ bit is set to 0, the output is high-Z.
If the LO/HIZ bit is set to 1, the output is
driven low.
Dither Control.
The J0 bit controls the
dither applied to the output. When J0 is
high, 2% peak dither is selected. When
J0 is low, 4% peak dither is selected.
f
O
/N
(f
O
/N) - 4%
0
f
O
/4096
DITHER RATE
2f
O
/4096
Bit 4:
WHERE N = (2
X
)
f
0
= FACTORY PROGRAMMED MASTER OSCILLATOR FREQUENCY
Figure 2. Output Frequency vs. Dither Rate
8
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DALLAS [ DALLAS SEMICONDUCTOR ]
