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DS1087LU-466 参数 Datasheet PDF下载

DS1087LU-466图片预览
型号: DS1087LU-466
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V扩频EconOscillator [3.3V Spread-Spectrum EconOscillator]
分类和应用: 振荡器
文件页数/大小: 12 页 / 154 K
品牌: DALLAS [ DALLAS SEMICONDUCTOR ]
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3.3V Spread-Spectrum EconOscillator
DS1087L
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
All voltages are referenced to ground.
This is the absolute accuracy of the master oscillator frequency at the default settings.
This is the change that is observed in master oscillator frequency with changes in voltage from nominal voltage at
T
A
= +25°C.
This is the percentage frequency change from the +25°C frequency due to temperature at V
CC
= 3.3V.
The dither deviation of the master oscillator frequency is unidirectional and lower than the undithered frequency.
This indicates the time elapsed between power-up and the output becoming active. An on-chip delay is intentionally
introduced to allow the oscillator to stabilize. t
stab
is equivalent to approximately 512 master clock cycles and depends
on the programmed master oscillator frequency.
Output voltage swings may be impaired at high frequencies combined with high output loading.
A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
> 250ns must then be met. This
is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line at least t
R MAX
+ t
SU:DAT
= 1000ns +
250ns = 1250ns before the SCL line is released.
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the V
IH MIN
of the SCL sig-
nal) to bridge the undefined region of the falling edge of SCL.
The maximum t
HD:DAT
need only be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
C
B
—total capacitance of one bus line, timing referenced to 0.9 x V
CC
and 0.1 x V
CC
.
Typical frequency shift due to aging is ±0.5%. Aging stressing includes Level 1 moisture reflow preconditioning (24hr
+125°C bake, 168hr 85°C/85%RH moisture soak, and 3 solder reflow passes +240 +0/-5°C peak) followed by 1000hr
max V
CC
biased 125°C HTOL, 1000 temperature cycles at -55°C to +125°C, and 168hr 121°C/2 ATM Steam/Unbiased
Autoclave.
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Typical Operating Characteristics
(V
CC
= 3.3V, T
A
= +25°C, unless otherwise noted.)
ACTIVE SUPPLY CURRENT
vs. TEMPERATURE
DS1087L toc01
ACTIVE SUPPLY CURRENT
vs. VOLTAGE
DS1087L toc02
SUPPLY CURRENT vs. PRESCALER
OUTPUT UNLOADED
6
5
CURRENT (mA)
4
3
2
1
0
3.6V
3.3V
2.7V
DS1087L toc03
7.5
V
CC
= 3.3V
FREQUENCY = 66.6MHz
OE = PDN = V
CC
15pF LOAD
8.0
7.0
6.0
CURRENT (mA)
5.0
4.0
3.0
2.0
1.0
FREQUENCY = 66.6MHz
OUTPUT UNLOADED
OE = PDN = V
CC
7
7.0
CURRENT (mA)
6.5
6.0
8.2pF LOAD
4.7pF LOAD
UNLOADED
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
5.5
5.0
0
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
VOLTAGE (V)
1
10
100
1000
PRESCALER (DECIMAL)
_____________________________________________________________________
5