DS1077U-100 参数 Datasheet PDF下载

DS1077

EN0 (bit)

(Default EN0 = 1)

1) If EN0 = 1 and PDN0 = 0 the CTRL0 pin functions as an Output Enable for OUT0, the frequency of

the output being determined by the SEL0 bit.

2) If PDN0 = 1, the EN0 bit is ignored, CTRL0 will function as a power-down, and output OUT0 will

always be enabled on power-up, its frequency being determined by the SEL0 bit.

3) If EN0 = 0 the function of CTRL0 is determined by the SEL0 and PDN0 bits (see Table 1).

SEL0

(Default SEL0 = 1)

1) If SEL0 = 1 and EN0 = PDN0 = 0, the CTRL0 pin determines the state of the MUX (i.e., the output

frequency of OUT0).

2) If CTRL0 = 0 the output will be the Master clock frequency.

3) If CTRL0 = 1 the output will be the output frequency of the M prescaler.

4) If either EN0 or PDN0 = 1 then SEL0 determines the frequency of OUT0 when it is enabled.

5) If SEL0 = 0 the output will be the Master clock frequency.

6) If SEL0 = 1 the output will be the output frequency of the M prescaler (see Table 1).

PDN0

(Default PDN0 = 0)

1) This bit (if set to 1) causes CTRL0 to perform a power-down function, regardless of the setting of the

other bits.

2) If PDN0 = 0 the function of CTRL0 is determined by the values of EN0 and SEL0.

NOTE:

When EN0 = SEL0 = PDN0 = 0, CTRL0 also functions as a power-down. This is a special case where all

the OUT0 circuitry is disabled even when the device is powered up for power to saving when OUT0 is

not used (see Table 1).

PDN1

1) If PDN1 = 1, CTRL1 will function as a power-down.

(Default PDN1 = 0)

2) If PDN1 = 0, CTRL1 functions as an output enable for OUT1 only (see Table 2.)

NOTE (ON OUTPUT ENABLE AND POWER-DOWN):

1) Both enables are “smart” and wait for the output to be low before going to Hi-Z.

2) Power-down sequence first disables both outputs before powering down the device.

3) On power-up the outputs are disabled until the clock has stabilized (~8000 cycles).

4) In power-down mode, the device cannot be programmed.

5) A power-down command must persist for at least two cycles of the lowest output frequency plus 10ms.

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