DS1077L
TABLE 5
BIT VALUE
0 000 000 000
*
0 0 00 0 00 001
—
—
—
—
1 111 111 111
*Default Condition
DIVISOR (N)
2
3
—
—
—
—
1025
BUS WORD
NAME
—
—
—
Factory Default
0*
0*
0*
*These bits are reserved and must be set to zero.
—
0*
WC
0
A2
0
A1
0
A0
0
A0, A1, A2
These are the device select bits that determine the address of the device.
(Default Setting = 000)
(Default Setting WC = 0)
WC
This bit determines when/if the EEPROM is written to after register contents have been changed.
If WC = 0, the EEPROM is automatically written after a write register command.
If WC = 1, the EEPROM is only written when the WRITE command is issued.
Regardless of the value of the WC bit, the value of the BUS register (A0, A1, and A2) is always
immediately written to the EEPROM.
2-WIRE SERIAL DATA BUS
The DS1077L supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls
the message is called a “master.” The devices that are controlled by the master are “slaves.” The bus must
be controlled by a master device that generates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions. The DS1077L operates as a slave on the 2-wire bus.
Connections to the bus are made via the open-drain I/O lines, SDA and SCL. A pullup resistor (5k) is
connected to SDA.
The following bus protocol has been defined (see Figure 2):
§
Data transfer may be initiated only when the bus is not busy.
§
During data transfer, the data line must remain stable whenever the clock line is high. Changes in
the data line while the clock line is high will be interpreted as control signals.
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