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DS1077LZ-60 参数 Datasheet PDF下载

DS1077LZ-60图片预览
型号: DS1077LZ-60
PDF下载: 下载PDF文件 查看货源
内容描述: 3V EconOscillator /分频器 [3V EconOscillator/Divider]
分类和应用:
文件页数/大小: 20 页 / 274 K
品牌: DALLAS [ DALLAS SEMICONDUCTOR ]
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DS1077L
TABLE 1
EN0
(BIT)
0
0
SEL0
(BIT)
0
1
PDN0
(BIT)
0
0
CTRL0
(PIN)
1
0
1
0
1
0
1
0
OUT0
CTRL0
(PIN)
FUNCTION
Hi-Z
(OUT1 and OUT2) Power-Down*
Hi-Z
DEVICE
MODE
Power-Down
Active
Master Clk/M
MUX Select
Active
Master Clk
Hi-Z
1
0
0
Output Enable
Active
Master Clk
Hi-Z
1
1
0
Output Enable
Active**
Master Clk/M
Hi-Z
1
Power-Down
(OUT1 and OUT2) Power-Down
X
0
1
0
Master Clk
Active
1
Hi-Z
Power-Down
X
1
1
Power-Down
0
Master Clk/M
Active
*This mode is for applications where OUT0 is not used, but CTRL0 is used as a device shutdown.
**Default Condition
CONTROL PIN 1 (CTRL1)
– A multifunctional input pin that can be selected as an output enable
and/or a power-down. Its function is determined by the user-programmable control register value of
PDN1. (See Table 2.)
TABLE 2
PDN1
(BIT)
0
0
1
1
CTRL1
(PIN)
0
1
0
1
CTRL1
FUNCTION
Output Enable
Output Enable
Power-Down
Power-Down
OUT 1
Out Clk
Hi-Z
Out Clk
Hi-Z
(OUT1 and OUT2)
DEVICE MODE
Active*
Active*
Active
Power-Down
*Default Condition
NOTE:
Both CTRL0 and CTRL1 can be configured as power-downs, they are internally “OR” connected so that
either of the control pins may be used to provide a power-down function for the whole device, subject to
appropriate settings of the PDN0 and PDN1 register bits. (See Table 3.)
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