DS1075
edge of SELX and the first rising edge of the externally derived clock is t SIE . Approximate maximum
and minimum values of these parameters are:
t
LOW
(min) = t
I
/2
t
LOW
(max) = 3t
I
/2 + t
Elow
t
SIE
(min) = t
I
/2
t
SIE
(max) = 3 t
I
/2 + t
Ehigh
NOTE:
In each case there will be a small additional delay due to internal propagation delays.
POWER-DOWN CONTROL
If the PDN bit is set to “1”, the
PDN
/
SELX
pin can be used to power-down the device. If
PDN
is high
the device will run normally.
POWER-DOWN
If
PDN
is taken low a power-down sequence is initiated. The “Enabling Sequencer” is used to execute
events in the following sequence:
1. Disable OUT (same sequence as when OE is used) and reset N counters.
2. When OUT is low, switch OUT to high-impedance state.
3. Disable MCLK (and OUT0 if
EN0
bit = 0), switch OUT0 to high impedance state.
4. Disable internal oscillator and OSCIN buffer.
POWER-UP
When
PDN
is taken to a high level the following power-up sequence occurs:
1. Enable internal oscillator and/or OSCIN buffer.
2. Set M and N to maximum values.
3. Wait approximately 256 cycles of MCLK for it to stabilize.
4. Reset M and N to programmed values.
5. Enable OUT0 (assuming
EN0
bit = 0).
6. Enable OUT.
Steps 2 through 4 exist to allow the oscillator to stabilize before enabling the outputs.
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DALLAS [ DALLAS SEMICONDUCTOR ]
