DS1075
Table 2
MSEL
E/ I
DIV1
M
BIT
BIT*
BIT
BIT
OPERATION
0
0
0
0
INTERNAL OSCILLATOR DIVIDED BY 4*N
0
0
0
1
INTERNAL OSCILLATOR DIVIDED BY 2*N
0
0
1
X
INTERNAL OSCILLATOR DIVIDED BY N
0
1
X
X
EXTERNAL OSCILLATOR DIVIDED BY N
1
0
X
X
INTERNAL OSCILLATOR DIVIDED BY 1
1
1
X
X
EXTERNAL OSCILLATOR DIVIDED BY 1
*Assuming PDN bit = 1, otherwise internal/external selection will be controlled by the
PDN
/
SELX
pin.
DIV WORD
Figure 3
(MSB)
N (9-BITS)
(LSB)
PDN
This bit is used to determine the function of the
PDN
/
SELX
pin. If PDN=0, the
PDN
/
SELX
pin can be
used to determine the timing reference (either the internal oscillator or an external reference/crystal). If
PDN=1, the
PDN
/
SELX
pin is used to put the device into power-down mode.
EN0
This bit is used to determine whether the OUT0 pin is active or not. If
EN0
=1, OUT0 is disabled (High-
impedance). If
EN0
=0, the internal reference clock (MCLK) is output from OUT0. The OE pin has no
effect on OUT0, but OUT0 is disabled as part of the power-down sequence.
N
These nine bits determine the value of the programmable divider. The range of divisor values is from 2 to
513, and is equal to the programmed value of N plus 2:
Table 3
BIT
VALUES
000000000
000000001
.
.
.
.
.
DIVISOR (N)
VALUE
2
3
.
.
.
.
.
111111111
513
NOTE:
The maximum value of N is constrained by the minimum output frequency. If the internal clock is
selected, INTOSC/(M*N) must be greater than f
OUTmin
; if the external clock is selected, EXTCLK/N must
be greater than f
OUTmin
. (If DIV1=1, then INTOSC or EXTCLK, as applicable, must exceed f
OUTmin
).
5 of 18
DALLAS [ DALLAS SEMICONDUCTOR ]
